PDF AS7C1026A Data sheet ( Hoja de datos )

Número de pieza	AS7C1026A
Descripción	5V/3.3V 64K X 16 CMOS SRAM
Fabricantes	Alliance Semiconductor Corporation
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No Preview Available ! January 2001 w w w . DAa dt avSahneceet 4IUn. cfoo mrmation ® 5V/3.3V 64K X 16 CMOS SRAM AS7C1026A AS7C31026A Features • AS7C1026A (5V version) • AS7C31026A (3.3V version) • Industrial and commercial versions • Organization: 65,536 words × 16 bits • Center power and ground pins for low noise • High speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time • Low power consumption: ACTIVE - 660 mW (AS7C1026A) / max @ 10 ns - 324 mW (AS7C31026A) / max @ 10 ns • Low power consumption: STANDBY - 55 mW (AS7C1026A) / max CMOS I/O - 36 mW (AS7C31026A) / max CMOS I/O • Latest 6T 0.25u CMOS technology • 2.0V data retention • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin 400 mil TSOP II - 48-ball 6 mm × 8 mm CSP mBGA • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram A0 A1 A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 I/O buffer WE UB OE LB CE 64K × 16 Array Control circuit Column decoder Pin arrangement 44-Pin SOJ, TSOP II (400 mil) VCC GND A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 A5 43 A6 42 A7 41 OE 40 UB 39 LB 38 I/O15 37 I/O14 36 I/O13 35 I/O12 34 GND 33 VCC 32 I/O11 31 I/O10 30 I/O9 29 I/O8 28 NC 27 A8 26 A9 25 A10 24 A11 23 NC 48-CSP mini Ball-Grid-Array Package 1 2 3 45 6 A LB OE A0 A1 A2 NC B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D VSS I/O11 NC E VDD I/O12 NC F I/O14 I/O13 A14 A7 I/O3 VDD NC I/O4 VSS A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC Selection guide Maximum address access time Maximum output enable access time AS7C1026A Maximum operating current AS7C31026A Maximum CMOS standby current AS7C1026A AS7C31026A AS7C1026A-10 AS7C31026A-10 10 3 120 90 10 10 AS7C1026A-12 AS7C31026A-12 12 3 110 80 10 10 AS7C1026A-15 AS7C31026A-15 15 4 100 80 10 10 AS7C1026A-20 AS7C31026A-20 20 5 100 80 15 15 Unit ns ns mA mA mA mA 2/6/01; V.0.9 Alliance Semiconductor P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. 1 page www.DataSheet4U.com AS7C1026A AS7C31026A ® Write cycle (over the operating range) 11 -10 -12 -15 -20 Parameter Symbol Min Max Min Max Min Max Min Max Unit Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select low to end of write tWC 10 – 12 – 15 – 20 – tCW 8 – 10 – 12 – 12 – tAW 8 – 9 – 10 – 12 – tAS 0 – 0 – 0 – 0 – tWP 7 – 8 – 9 – 12 – tAH 0 – 0 – 0 – 0 – tDW 5 – 6 – 8 – 10 – tDH 0 – 0 – 0 – 0 – tWZ – 6 – 6 – 6 – 8 tOW 1 – 1 – 1 – 2 – tBW 8 – 10 – 12 – 12 – ns ns ns ns ns ns ns ns ns ns ns Write waveform 1 (WE controlled)10,11 Address CE LB, UB tAS tWC tCW tBW tAW tWP tWR WE DataIN DataOUT Data undefined tWZ Write waveform 2 (CE controlled)10,11 Address CE tAS LB, UB tWC tCW tAW tBW WE tDW Data valid tDH tOW high Z tWR tWP tDW tDH DataIN DataOUT tCLZ high Z tWZ Data undefined Data valid high Z tOW Notes 5 4, 5 4, 5 2/6/01; V.0.9 Alliance Semiconductor P. 5 of 9 5 Page

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