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PDF PSMN3R0-30YL Data sheet ( Hoja de datos )
| Número de pieza | PSMN3R0-30YL | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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PSMN3R0-30YL
N-channel TrenchMOS logic level FET
Rev. 01 — 10 September 2008
Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
- - 30 V
ID drain current
Tmb = 25 °C; VGS = 10 V; [1] - - 100 A
see Figure 1;
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
- - 81 W
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
- 5.1 - nC
Static characteristics
RDSon drain-source
on-state resistance
VGS = 10 V; ID = 15 A;
Tj = 25 °C; see Figure 12
-
2.15 3
mΩ
[1] Continuous current is limited by package.
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PSMN3R0-30YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C; see
Figure 10; see Figure 11
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C; see
Figure 10
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C; see
Figure 12
VGS = 10 V; ID = 15 A; Tj = 150 °C; see
Figure 13
VGS = 10 V; ID = 15 A; Tj = 25 °C; see
Figure 12
RG gate resistance
Dynamic characteristics
f = 1 MHz
QG(tot)
total gate charge
ID = 10 A; VDS = 12 V; VGS = 10 V; see
Figure 14; see Figure 15
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see
Figure 14
QGS
QGD
QGS(th)
gate-source charge
gate-drain charge
pre-threshold
gate-source charge
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see
Figure 14; see Figure 15
QGS(th-pl)
post-threshold
gate-source charge
VGS(pl)
gate-source plateau VDS = 12 V; see Figure 14; see Figure 15
voltage
Ciss
Coss
Crss
input capacitance
output capacitance
reverse transfer
capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
td(on)
tr
td(off)
tf
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
PSMN3R0-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
Min Typ Max Unit
30 -
27 -
1.3 1.7
-V
-V
2.15 V
0.65 -
-
V
--
2.45 V
- - 1 µA
--
100 µA
--
100 nA
--
100 nA
-
2.98 4.8
mΩ
--
5.2 mΩ
- 2.15 3
mΩ
- 0.55 -
Ω
- 45.8 -
nC
- 43 -
- 21 -
nC
nC
- 7.02 -
- 5.1 -
- 4.74 -
nC
nC
nC
- 2.28 -
nC
- 2.37 -
V
- 2822 -
- 615 -
- 260 -
pF
pF
pF
- 34 -
- 58 -
- 50 -
- 21 -
ns
ns
ns
ns
© NXP B.V. 2008. All rights reserved.
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PSMN3R0-30YL
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID
Release date
PSMN3R0-30YL_1
20080910
Data sheet status
Preliminary data sheet
Change notice
-
Supersedes
-
PSMN3R0-30YL_1
Preliminary data sheet
Rev. 01 — 10 September 2008
© NXP B.V. 2008. All rights reserved.
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