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ST9040 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer ST9040
Beschreibung 16K ROM HCMOS MCU
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
ST9040 Datasheet, Funktion
www.DataSheet4U.com
® ST9040
16K ROM HCMOS MCU
WITH EEPROM, RAM AND A/D CONVERTER
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time : 500ns
(12MHz internal)
Internal Memory :
ROM
16K bytes
RAM
256 bytes
EEPROM
512 bytes
224 general purpose registers available as RAM,
accumulators or index registers (register file)
80-pin PQFP package for ST9040Q
68-lead PLCC package for ST9040C
DMA controller, Interrupt handler and Serial Pe-
ripheral Interface as standard features
Up to 56 fully programmable I/O pins
Up to 8 external plus 1 non-maskableinterrupts
16 bit Timer with 8 bit Prescaler, able to be used
as a WatchdogTimer
Two 16 bit Multifunction Timers, each with an 8
bit prescaler and 13 operating modes
8 channel 8 bit Analog to Digital Converter, with
Analog Watchdogs and external references
Serial Communications Interface with asynchro-
nous and synchronous capability
Rich Instruction Set and 14 Addressingmodes
Division-by-Zero trap generation
Versatile developmenttools, including assembler,
linker, C-compiler, archiver, graphic oriented de-
buggerand hardware emulators
Real Time Operating System
Windowed and One Time Programmable EPROM
parts available for prototyping and pre-production
development phases
Pin to pin compatible with ST9036
PQFP80
PLCC68
(Ordering Information at the end of the Datasheet)
February 1997
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ST9040 Datasheet, Funktion
www.DataSheet4U.com
ST9040
1.2 PIN DESCRIPTION
AS. Address Strobe (output, active low, 3-state).
Address Strobe is pulsed low once at the begin-
ning of each memory cycle. The rising edge of AS
indicates that address, Read/Write (R/W), and
Data Memory signals are valid for program or data
memory transfers. Under program control, AS can
be placed in a high-impedance state along with
Port 0 and Port 1, Data Strobe (DS) and R/W.
DS. Data Strobe (output, active low, 3-state). Data
Strobe provides the timing for data movement to or
from Port 0 for each memory transfer. During a
write cycle, data out is valid at the leading edge of
DS. During a read cycle, Data In must be valid prior
to the trailing edge of DS. When the ST9040 ac-
cesses on-chip memory, DS is held high during the
whole memory cycle. It can be placed in a high im-
pedancestate alongwith Port 0, Port 1, AS and R/W.
R/W. Read/Write (output, 3-state). Read/Write
determines the direction of data transfer for exter-
nal memory transactions. R/W is low when writing
to external program or data memory, and high for
all other transactions. It can be placed in a high im-
pedancestate along with Port 0, Port 1, AS and DS.
RESET. Reset (input, active low). The ST9 is initial-
isedby the Reset signal. With the deactivationof RE-
SET, program execution begins from the Program
memory location pointed to by the vector contained
in program memory locations 00h and 01h.
INT0, INT7. External interrupts (input, active on ris-
ing or falling edge). External interrupt inputs 0 and
Figure 3. ST9040 Block Diagram
7 respectively. INT0 channel may also be used for
the timer watchdog interrupt.
OSCIN, OSCOUT. Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the in-
put of the oscillator inverter and internal clock gen-
erator; OSCOUT is the output of the oscillator
inverter.
AVDD. AnalogVDD ofthe Analogto Digital Converter.
AVSS. Analog VSS of the Analog to Digital Con-
verter. Must be tied to VSS.
VDD. Main Power Supply Voltage (5V ± 10%)
VSS. Digital Circuit Ground.
P0.0-P0.7, P1.0-P1.7, P2.0-P2.7 P3.0-P3.7, P4.0-
P4.7, P5.0-P5.7, P7.0-P7.7 I/O Port Lines (In-
put/Output, TTL or CMOS compatible). 56 lines
grouped into I/O ports of 8 bits, bit programmable
under program control as general purpose I/O or
as alternate functions.
1.2.1 I/O Port Alternate Functions
Each pin of the I/O ports of the ST9040 may as-
sume software programmable Alternative Func-
tions as shown in the Pin Configuration Drawings.
Table 1-3 shows the Functions allocated to each
I/O Port pins and a summary of packagesfor which
they are available.
16k Bytes
ROM
512 Bytes
EEPROM
IN T0 INT7
256 Bytes
RAM
256 Bytes
REGISTER FILE
16-Bit TIMER / WATCHDOG + SPI
CPU
SCI
WITH DMA
8
I/O PORT 7
( SCI )
MEMORY BUS
REGISTER BUS
I/O PORT 0
( Address/Data )
I/O PORT 1
( Address )
I/O PORT 2
( SPI )
I/O PORT 3
( TIMERS )
8 888
2 x 16-bi t TIMER
W ITH DMA
I/O PORT 4
( Analog Inputs )
8
A/D
CONVERTER
I/O PORT 5
WITH HANDSHAKE
AVD D AVS S
8
V R0 0 1 3 85
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®

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ST9040 pdf, datenblatt
www.DataSheet4U.com
ST9040
EEPROM (Continued)
1.3.2.7 EEPROM Control Register
EECR R241 (F1h) Page 0 Read/Write
(except EEBUSY: read only)
EEPROM Control Register
Reset value : 0000 0000b (00h)
7
0
0 VERIFY EESTBY EEIEN PLLST PLLEN EEBUSY EEWEN
bit 7 = B7: This bit is forced to “0” after reset and
MUST not be modified by the user.
bit 6 = VERIFY: Set Verify mode. Verify (active
high) is used to activate the verify mode.
The verify mode provides a guarentee of good re-
tention of the programmed bit. When active, the
reading voltage on the cell gate is decreased from
1.2V to 0.0V, decreasing the current from the pro-
grammed cell by 20%. If the cell is well pro-
grammed (to “1”), a “1” will still be read, otherwise
a “0” will be read.
Note . The verify mode must not be used during an
erasing or a programming cycle).
bit 5 = EESTBY: EEPROM Stand-By. EESTBY =
“1” switches off all power consumption sources in-
side the EEPROM. Any attempt to access the
EEPROM when EESTBY = “1” will produce unpre-
dictable results.
Table 1-5. Register Map Addendum
Note. After EESTBY is reset, the user must wait 6
CPUCLK cycles (e.g. 1 nop instruction) before se-
lecting the EEPROM.
bit 4 = EEIEN: EEPROM Interrupt Enable. INTEN
= “1” disables the external interrupt source INT4,
and enables the EEPROM to send its interrupt re-
quest to the central interrupt unit at the end of each
write procedure.
bit 3 = PLLST: Parallel Write Start. Setting PLLST
to “1” starts the parallel writing procedure.It can be
set only if PLLEN is alreadyset. PLLST is internally
reset at the end of the programming sequence.
bit 2 = PLLEN: Parallel write Enable. Setting
PLLEN to “1” enables the parallel writing mode
which allows the user to write up to 16 bytes at the
same time. PLLEN is internally reset at the end of
the programming sequence.
bit 1 = EEBUSY: BUSY. When this read only bit is
high, an EEPROM write operation is in progress
and any attempt to access the EEPROM is
aborted.
bit 0 = EEWEN: EEPROM Write Enable. Setting
this bit allows programming of the EEPROM, when
low a writing attempt has no effect.
1.3.3 REGISTER MAP
Please refer to the Register Map of the ST9036 for
all general registers with the exceptionof the regis-
ter shown in the following table.
EECR R241
(F1h)
Page 0 Read/Write
Control Registers
Figure 1-5. EEPROM Parallel Programming Rows
12/56
®

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