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PDF CY7C1416BV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1416BV18 | |
| Descripción | (CY7C14xxBV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1416BV18, CY7C1427BV18
CY7C1418BV18, CY7C1420BV18
36-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
Functional Description
■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
■ 267 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 534 MHz) at 267 MHz for DDR-II
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Synchronous internally self-timed writes
■ DDR-II operates with 1.5 cycle read latency when DLL is
enabled
■ Operates as a DDR-I device with 1 cycle read latency in DLL
off mode
■ 1.8V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4V–VDD)
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both in Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and
CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1416BV18
and two 9-bit words in the case of CY7C1427BV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1416BV18 and
CY7C1427BV18. On CY7C1418BV18 and CY7C1420BV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1418BV18 and two 36-bit words in the case of
CY7C1420BV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Configurations
CY7C1416BV18 – 4M x 8
CY7C1427BV18 – 4M x 9
CY7C1418BV18 – 2M x 18
CY7C1420BV18 – 1M x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
267 MHz
267
x8 795
x9 800
x18 835
x36 910
250 MHz
250
725
725
760
825
200 MHz
200
600
600
620
675
167 MHz
167
500
500
525
570
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-07033 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 27, 2007
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CY7C1416BV18, CY7C1427BV18
CY7C1418BV18, CY7C1420BV18
Pin Configuration (continued)
The pin configuration for CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 follow. [1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1418BV18 (2M x 18)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
R/W
BWS1
K NC/144M LD
A
A
B
NC DQ9 NC
A NC/288M K
BWS0
A
NC NC
C
NC NC NC VSS
A
A0
A VSS NC DQ7
D NC NC DQ10 VSS VSS VSS VSS VSS NC NC
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ NC
NC
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ4
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC DQ15 NC
VDDQ
VSS
VSS
VSS VDDQ NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC DQ1
N NC NC DQ16 VSS A A A VSS NC NC
P
NC
NC DQ17
A
A
C
A
A NC NC
R
TDO
TCK
A
A
A
C
A
A
A TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1420BV18 (1M x 36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ NC/144M A
R/W
BWS2
K
BWS1
LD
A NC/72M CQ
B NC DQ27 DQ18 A BWS3 K BWS0 A NC NC DQ8
C
NC NC DQ28 VSS
A
A0
A VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS VDDQ NC DQ15 DQ6
F
NC DQ30 DQ21 VDDQ VDD
VSS
VDD
VDDQ
NC
NC DQ5
G
NC DQ31 DQ22 VDDQ VDD
VSS
VDD
VDDQ
NC
NC DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC DQ13 DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC DQ12 DQ3
L
NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC
NC DQ2
M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
N NC DQ35 DQ25 VSS A A A VSS NC NC DQ10
P
NC
NC DQ26
A
A
C
A
A
NC
DQ9
DQ0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 001-07033 Rev. *C
Page 5 of 29
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CY7C1416BV18, CY7C1427BV18
CY7C1418BV18, CY7C1420BV18
Write Cycle Descriptions
The write cycle description table for CY7C1427BV18 follows. [2, 8]
BWS0
L
L
H
K
L–H
–
L–H
K
– During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
– No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1420BV18 follows. [2, 8]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Document Number: 001-07033 Rev. *C
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