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PDF ZL30142 Data sheet ( Hoja de datos )
| Número de pieza | ZL30142 | |
| Descripción | SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL30142
SyncE SONET/SDH
G.8262/Stratum 3 System Synchronizer
Short Form Data Sheet
Features
• Supports the requirements of ITU-T G.8262 for
synchronous Ethernet Equipment slave Clocks
(EEC option 1 and 2)
• Supports the requirements of Telcordia GR-1244
Stratum 3 and GR-253, ITU-T G.812, G.813
• Supports ITU-T G.823, G.824 and G.8261 for 2048
kbit/s and 1544 kbit/s interfaces
• Meets the SONET/SDH jitter generation
requirements up to OC-48/STM-16
• Synchronizes to telecom reference clocks (2 kHz,
N*8 kHz up to 77.76 MHz, 155.52 MHz) or to
Ethernet reference clocks (25 MHz, 50 MHz,
62.5 MHz, 125 MHz)
• Generates standard SONET/SDH clock rates (e.g.,
19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
622.08 MHz) or Ethernet clock rates (e.g., 25 MHz,
50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for
synchronizing Gigabit Ethernet PHYs
• Programmable output synthesizer generates
telecom clock frequencies from any multiple of
8 kHz up to 100 MHz
• Generates several styles of telecom frame pulses
with selectable pulse width, polarity and frequency
• Internal state machine automatically controls mode
of operation (free-run, locked, holdover)
February 2009
Ordering Information
ZL30142GGG 64 Pin CABGA
ZL30142GGG2 64 Pin CABGA*
*Pb Free Tin/Silver/Copper
-40oC to +85oC
Trays
Trays
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Provides automatic reference switching and
holdover during loss of reference input
• Supports master/slave configuration and dynamic
input to output delay compensation for
AdvancedTCATM
• Configurable input to output delay and output to
output phase alignment
Applications
• ITU-T G.8262 System Timing Cards which support
1 GbE interfaces
• Telcordia GR-253 Carrier Grade SONET/SDH
Stratum 3 System Timing Cards
ref0
ref1
ref2
sync0
sync1
sync2
/N1
/N2
osci osco
ref
DPLL
sync
SONET/
Ethernet
APLL
Programmable
Synthesizer
N*8kHz
diff
apll_clk
p_clk
p_fp
mode lock hold
I2C/SPI
JTAG
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet ZL30142.PDF ] | |
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