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PDF ISL6265A Data sheet ( Hoja de datos )
| Número de pieza | ISL6265A | |
| Descripción | Multi-Output Controller | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
May 11, 2009
ISL6265A
FN6884.0
Multi-Output Controller with Integrated
MOSFET Drivers for AMD SVI Capable
Mobile CPUs
The ISL6265A is a multi-output controller with embedded
gate drivers. A single-phase controller powers the
Northbridge (VDDNB) portion of the CPU. The two
remaining controller channels can be configured for
two-phase or individual single-phase outputs. For uniplane
CPU applications, the ISL6265A is configured as a
two-phase buck converter. This allows the controller to
interleave channels to effectively double the output voltage
ripple frequency, and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller area. For dual-plane
processors, the ISL6265A can be configured as independent
single-phase controllers powering VDD0 and VDD1.
The heart of the ISL6265A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional buck regulator, the R3 Technology™ has a
faster transient response. This is due to the R3 modulator
commanding variable switching frequency during a load
transient.
The Serial VID Interface (SVI) allows dynamic adjustment of
the Core and Northbridge output voltages independently and
in combination from 0.500V to 1.55V. Core and Northbridge
output voltages achieve a 0.5% system accuracy
over-temperature.
A unity-gain differential amplifier is provided for remote CPU
die sensing. This allows the voltage on the CPU die to be
accurately regulated per AMD mobile CPU specifications.
Core output current sensing is realized using lossless
inductor DCR sensing. All outputs feature overcurrent,
overvoltage and undervoltage protection.
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE PKG.
(Pb-Free) DWG. #
ISL6265AHRTZ 6265A HRTZ -10 to +100 48 Ld 6x6 TQFN L48.6x6
ISL6265AHRTZ-T* 6265A HRTZ -10 to +100 48 Ld 6x6 TQFN L48.6x6
Tape and Reel
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020
Features
• Core Configuration Flexibility
- Dual Plane, Single-Phase Controllers
- Uniplane, Two-Phase Controller
• Precision Voltage Regulators
- 0.5% System Accuracy Over-temperature
• Voltage Positioning with Adjustable Load Line and Offset
• Internal Gate Drivers with 2A Driving Capability
• Differential Remote CPU Die Voltage Sensing
• Core Differential Current Sensing: DCR or Resistor
• Northbridge Lossless rDS(ON) Current Sensing
• Serial VID Interface
- Two Wire Clock and Data Bus
- Supports High-Speed I2C
- 0.500V to 1.55V in 12.5mV Steps
- Supports PSI_L Power-Saving Mode
• Core Outputs Feature Phase Shedding with PSI_L
• Adjustable Output-Voltage Offset
• Digital Soft-Start of all Outputs
• User Programmable Switching Frequency
• Static and Dynamic Current Sharing (Uniplane Core)
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free (RoHS compliant)
Pinout
ISL6265A
(48 LD 6X6 TQFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
OFS/VFIXEN 1
PGOOD 2
PWROK 3
SVD 4
SVC 5
ENABLE 6
RBIAS 7
OCSET 8
VDIFF0 9
FB0 10
COMP0 11
VW0 12
49
GND
[BOTTOM]
36 BOOT_NB
35 BOOT0
34 UGATE0
33 PHASE0
32 PGND0
31 LGATE0
30 PVCC
29 LGATE1
28 PGND1
27 PHASE1
26 UGATE1
25 BOOT1
13 14 15 16 17 18 19 20 21 22 23 24
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6265A
www.SDaitmaSpheleift4iUe.dcomApplication Circuit for Dual Layout
+5V VIN
SVI DATA
SVI CLOCK
ENABLE
PWROK
VDDPWRGD
VCC PVCC
SVD
SVC
EN
PWROK
PGOOD
REMOTE
SENSE
VDD_PLANE_STRAP
+1.8V
REMOTE
SENSE
DNP UNIPLANE
VSEN0
RTN0
RTN1
VSEN1
OFS/VFIXEN
GND
UGATE0
BOOT0
PHASE0
LGATE0
PGND0
ISP0
ISN0
RBIAS
OCSET
VDIFF0
FB0
COMP0
VW0
VDIFF1
ISL6265A
UGATE1
BOOT1
PHASE1
LGATE1
PGND1
ISP1
ISN1
FB1
COMP1
VW1
FSET_NB
COMP_NB
FB_NB
UGATE_NB
BOOT_NB
PHASE_NB
LGATE_NB
PGND_NB
OCSET_NB
VSEN_NB
RTN_NB
+VIN
CIN
LOUT
VDD0
CORE
LOAD
+VIN
CIN
LOUT
+VIN
CIN
LOUT
UNIPLANE
VDD0
DNP
DUAL
PLANE
VDD1
CORE
LOAD
VDDNB
NB
LOAD
FIGURE 4. ISL6265A BASED UNIPLANE OR DUAL PLANE CORE CONVERTER WITH INDUCTOR DCR CURRENT SENSING
5 FN6884.0
May 11, 2009
5 Page 
ISL6265A
www.aDnateaSrrhoereat4mUp.cliofimer that allows the controller to maintain a
0.5% voltage regulation accuracy throughout the VID range
from 0.75V to 1.55V. Voltage regulation accuracy is slightly
wider, ±5mV, over the VID range from 0.7375V to 0.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients result in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. In uniplane configurations, transient load current
is inherently shared between active phases due to the use of
a common hysteretic window voltage. Individual average
phase currents are monitored and controlled to equally
share current among the active phases.
Modulator
The ISL6265A modulator features Intersil’s R3 technology, a
hybrid of fixed frequency PWM control and variable frequency
hysteretic control (see Figure 5). Intersil’s R3 technology can
simultaneously affect the PWM switching frequency and PWM
duty cycle in response to input voltage and output load
transients. The R3 modulator synthesizes an AC signal VR,
which is an analog representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The current
through CR is provided by a transconductance amplifier gm
that measures the VIN and VO voltages. The positive slope of
VR can be written as determined by Equation 1:
VRPOS = (gm) ⋅ (VIN – VOUT)
(EQ. 1)
The negative slope of VR can be written as determined by
Equation 2:
VRNEG = gm ⋅ VOUT
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 6 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; it is inversely proportional to the voltage
between VW and VCOMP.
Initialization
Once sufficient bias is applied to the VCC pin, internal logic
checks the status of critical pins to determine the controller
operation profile prior to ENABLE. These pins include RTN1
which determines single vs two-phase operation and
OFS/VFIXEN for enabling/disabling the SVI interface and
core voltage droop. Depending on the configuration set by
these pins, the controller then checks the state of the SVC
and SVD pins to determine the soft-start target output
voltage level..
VIN
+
gmVIN
VO +
gmVO
PWM FREQUENCY
CONTROL
+
V- W
+
VR
+
-
CR TO VCOMP +
PWM
CONTROL
FSET
R
PWM Q
S
ISL6265A
FIGURE 5. MODULATOR CIRCUITRY
RIPPLE CAPACITOR VOLTAGE CR
WINDOW VOLTAGE VW
ERROR AMPLIFIER VOLTAGE VCOMP
PWM
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Power-On Reset
The ISL6265A requires a +5V input supply tied to VCC and
PVCC to exceed a rising power-on reset (POR) threshold
before the controller has sufficient bias to guarantee proper
operation. Once this threshold is reached or exceeded, the
ISL6265A has enough bias to begin checking RTN1,
OFS/VFIXEN, ENABLE, and SVI inputs. Hysteresis between
the rising the falling thresholds assure the ISL6265A will not
inadvertently turn-off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 8).
Core Configuration
The ISL6265A determines the core channel requirements of
the CPU based on the state of the RTN1 pin prior to ENABLE. If
RTN1 is low prior to ENABLE, both VDD0 and VDD1 core
planes are required. The core controllers operate as
independent single-phase regulators. RTN1 is connected to the
CPU Core1 negative sense point. For single core CPU designs
(uniplane), RTN1 is tied to a +1.8V or greater supply. Prior to
ENABLE, RTN1 is detected as HIGH and the ISL6265A drives
the core controllers as a two-phase multi-phase regulator. Dual
purpose motherboard designs should include resistor options to
11 FN6884.0
May 11, 2009
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ISL6265A.PDF ] | |
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