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PDF STF5N95K3 Data sheet ( Hoja de datos )

Número de pieza STF5N95K3
Descripción Power MOSFETs
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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STD5N95K3, STF5N95K3
STP5N95K3, STU5N95K3
N-channel 950 V, 2.5 , 3.5 A, DPAK, TO-220, TO-220FP, IPAK
SuperMESH3™ Power MOSFET
Preliminary data
Features
Type
STD5N95K3
STF5N95K3
STP5N95K3
STU5N95K3
VDSS RDS(on) max ID
950 V < 3 3.5 A
950 V < 3 3.5 A
950 V < 3 3.5 A
950 V < 3 3.5 A
Pw
90 W
25 W
90 W
90 W
100% avalanche tested
Extremely large avalanche performance
Gate charge minimized
Very low intrinsic capacitances
Zener-protected
Application
Switching applications
Description
The new SuperMESH3™ series of power
MOSFETS is the result of the fine-tuning of ST's
well-established strip-based PowerMESH™
layout with a new optimized vertical structure. The
innovative design offer significantly reduced on-
resistance, exceptional dynamic performance and
very large avalanche capability, making the device
suitable for the most demanding applications.
3
2
1
TO-220
3
2
1
TO-220FP
IPAK
3
2
1
3
1
DPAK
Figure 1. Internal schematic diagram
D(2)
G(1)
S(3)
AM01476v1
Table 1. Device summary
Order code
STD5N95K3
STF5N95K3
STP5N95K3
STU5N95K3
Marking
5N95K3
5N95K3
5N95K3
5N95K3
Package
DPAK
TO-220FP
TO-220
IPAK
Packaging
Tape and reel
Tube
Tube
Tube
May 2009
Doc ID 15696 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/13
www.st.com
13

1 page




STF5N95K3 pdf
www.DataSShTeeDt45UN.c9o5mK3, STF5N95K3, STP5N95K3, STU5N95K3
Electrical characteristics
Table 6.
Symbol
Switching times
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
VDD = 475 V, ID = 1.75 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 2)
Min. Typ. Max Unit
TBD ns
TBD ns
--
TBD ns
TBD ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min. Typ. Max Unit
ISD
ISDM (1)
VSD (2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 3.5 A, VGS = 0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3.5 A, di/dt = 100 A/µs
VDD= 60 V
(see Figure 4)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3.5 A, di/dt = 100 A/µs
VDD= 60 V TJ = 150 °C
(see Figure 4)
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
3.5 A
-
14 A
- 1.5 V
TBD
- TBD
TBD
ns
µC
A
TBD
- TBD
TBD
ns
µC
A
Table 8.
Symbol
Gate-source Zener diode
Parameter
Test conditions
BVGSO
Gate-source breakdown
voltage
Igs=± 1 mA (open drain)
Min. Typ. Max. Unit
30 -
-V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
Doc ID 15696 Rev 1
5/13

5 Page





STF5N95K3 arduino
www.DataSShTeeDt45UN.c9o5mK3, STF5N95K3, STP5N95K3, STU5N95K3
Package mechanical data
DIM.
A
A1
b
b2
b4
c
c2
D
E
e
e1
H
L
(L1)
L2
V1
TO-251 (IPAK) mechanical data
min.
2.20
0.90
0.64
mm.
typ
5.20
0.45
0.48
6.00
6.40
2.28
4.40
16.10
9.00
0.80
0.80
10 o
max.
2.40
1.10
0.90
0.95
5.40
0.60
0.60
6.20
6.60
4.60
9.40
1.20
0068771_H
Doc ID 15696 Rev 1
11/13

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