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FAN2103 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FAN2103
Beschreibung 24V Input Integrated Synchronous Buck Regulator
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 14 Seiten
FAN2103 Datasheet, Funktion
December 2007
www.datasheet4u.com
FAN2103 — TinyBuck™
3A, 24V Input Integrated Synchronous Buck Regulator
Features
ƒ Over 95% efficiency
ƒ Internal power MOSFETs:
High-side RDS(ON) = 31mΩ
Low-side RDS(ON) = 23mΩ
ƒ Integrated low-side Schottky diode
ƒ Programmable frequency operation up to 750KHz
ƒ Power-good signal
ƒ Wide input range: 3.0V to 24V
ƒ Output voltage range: 0.8V to 90%VIN
ƒ Input under-voltage lockout (UVLO)
ƒ Programmable over-current protection
ƒ Under-voltage, over-voltage, and thermal protection
ƒ Selectable light-load power-saving mode
ƒ 5x6mm, 25-pin, 3-pad MLP
Applications
ƒ Thin and light Notebook PCs
ƒ Graphics cards
ƒ Battery-powered equipment
ƒ Set-top box
ƒ Point-of-load regulation
Description
The FAN2103 TinyBuck™ is an easy-to-use, cost- and
space-efficient, synchronous buck solution. It enables
designers to solve high-current requirements in a small
area with minimal external components.
External programming of clock frequency, current limit,
and loop response allows for optimization and flexibility
selecting output filter components and transient response.
The summing current mode modulator uses lossless
current sensing for current feedback and over-current,
and includes voltage feedforward.
Fairchild’s advanced BiCMOS power process,
combined with a thermally efficient MLP package,
provides low-RDS(ON), internal MOSFETs, and the ability
to dissipate high power in a small package.
Under-voltage, thermal shutdown, and power-good are
blanked at start-up, but protect the device from damage
during fault conditions.
Related Application Notes
ƒ AN-5067 – PCB land pattern design and surface
mount guidelines for MLP packages
Ordering Information
Part Number
FAN2103MPX
FAN2103EMPX
Operating
Temperature Range
-10°C to 85°C
-40°C to 85°C
Package
Packing Method
25-Pin Molded Leadless Package (MLP) 5x6mm Tape and Reel
25-Pin Molded Leadless Package (MLP) 5x6mm Tape and Reel
All packages are lead free per JEDEC: J-STD-020B standard.
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
www.fairchildsemi.com






FAN2103 Datasheet, Funktion
Electrical Specifications (Continued)
Recommended operating conditions are the result of using the circuit shown in Figure 1 unless otherwise noted.
Parameter
Soft-Start
www.datashVeeOtU4Tu.tcooRmegulation (T0.8)
Fault Enable/SSOK (T1.0)
Control Functions
EN Threshold, Rising
EN Hysteresis
EN Pull-up Resistance
EN Discharge Current
FB OK Drive Resistance
PGOOD Threshold
PGOOD Output Low
PGOOD Output High
PWM# Threshold
PWM# Input Current
Conditions
Frequency = 600KHz
Auto-restart Mode
FB < VREF
FB > VREF
IOUT < 2mA
VPGOOD = 5V
VPWM# = 0.4V
Min. Typ. Max. Unit
5.3 ms
6.7 ms
1.35 2.00
V
250 mV
800 KΩ
1 µA
800 Ω
-14 -11 -8 %VFB
107 110 113 %VFB
0.4 V
1 µA
0.6 0.8 V
1.0 1.2 µA
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
6
www.fairchildsemi.com

6 Page









FAN2103 pdf, datenblatt
Table 1. Fault / Restart Provisioning
EN pin
Controller / Restart State
Pull to GND OFF (disabled)
VCC
Open
www.datasheet4u.com
Cap to GND
No restart – latched OFF
Immediate restart after fault
New soft-start cycle after:
tDELAY (msec) = 3.9 C(nf)
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin to the VCC
pin or drive it with a logic gate to keep the 1µA current
sink from discharging EN to 1.1V.
During power-saving mode, the output is regulated to a
slightly higher value than its set point, since the current
pulse is triggered when FB crosses VREF.
The IC is prevented from switching in the audible band.
If the FB pin has not dropped to VREF within 40µs of the
last pulse, the IC sinks current through the inductor to
initiate a new cycle.
Transition back to PWM mode is achieved when a load
transient causes the output voltage to drop 1.5% below
its regulation point.
1.85
1.84
1.83
1.82
1.81
1.8
PWM to PSM
Transition
1.79
1.78
0
0.25
0.5
0.75
PSM to PWM
PWM to PSM
PSM to PWM
Transition
1 1.25 1.5
Figure 24. Fault Latch with Delayed Auto-Restart
Over-Temperature Protection
FAN2103 incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 160°C is reached. The IC is allowed to restart
when the die temperature falls below 130°C.
Figure 25. Power-Saving Mode Regulation
(Using Figure 10 Circuit)
Power-saving mode operation can be disabled by
connecting the PWM# pin to AGND, allowing only PWM
operation. The PWM# pin has a 1µA pull-down. If <0.6V
is detected, power-saving mode operation is disabled.
PCB Layout
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW
when VOUT is out of regulation, as measured at the FB
pin (thresholds are specified in the Electrical
Specifications section). PGOOD does not assert HIGH
until the fault latch is enabled (T1.0).
Power-Saving Mode
The FAN2103 maintains high efficiency at light load by
changing to a discontinuous, constant peak current,
power-saving mode (PSM).
The transition to power-saving mode occurs when the load
is <ΔIL/2 for eight consecutive clock cycles.
In power-saving mode, a constant-peak inductor current
(ΔILPSM) is generated each on-cycle. ΔILPSM is nominally
85% larger than PWM-mode inductor ripple (ΔIL).
Figure 26. Recommended PCB Layout
© 2007 Fairchild Semiconductor Corporation
FAN2103 Rev. 1.0.3
12
www.fairchildsemi.com

12 Page





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