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PDF AN95102 Data sheet ( Hoja de datos )
| Número de pieza | AN95102 | |
| Descripción | Low Power Single/Dual Ferquency Synthesizers | |
| Fabricantes | Philips | |
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Philips Semiconductors
Low power single/dual frequency synthesizers:
UMA1017M/1018M/1019M(AM)/1020M(AM)
Application note
AN95102
Author: P. Hugues
UMA1018M and UMA1020M/UMA1020AM low power dual frequency synthesizers
UMA1017M and UMA1019M/UMA1019AM low power single frequency synthesizers
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This application note describes the UMA1018M and
UMA1020M/UMA1020AM from Philips Semiconductors. They
permit a low-voltage low-power single-chip solution to designing
dual PLL frequency synthesizers. They are intended for use in
digital or analogue wireless communications equipment. Typical
applications include GSM, DECT and DCS1800.
Three low-voltage low-power solutions to single frequency
synthesizers are also briefly described. The UMA1017M and
UMA1019M/UMA1019AM are derivatives from UMA1018M and
UMA1020M, respectively, and are hence closely related.
The overall performance of any PLL frequency synthesizer system
is critically determined by the low pass filter used. Described in this
report is a basic loop filter design method with worked examples and
some measurement results.
1. INTRODUCTION TO UMA1018M DUAL
SYNTHESIZER
1.1 General description
The UMA1018M [1] is a low power low voltage single chip solution
to a dual frequency synthesizer used in radiocommunications.
Designed in a BICMOS process, it operates from 2.7 (3 NiCd cells)
to 5.5 V. The UMA1018M contains all the necessary elements with
the exception of the VTCXO, VCO and loop filters to build two PLL
frequency synthesizers.
It is intended that the principal synthesizer operates in the 50 to
1250 MHz range, and the auxiliary synthesizer will work between 20
and 300 MHz. For each synthesizer, fully programmable main and
reference dividers are integrated on chip. The reference input
FXTAL can operate from 5 to 40 MHz. Fast programming is
possible via the three wire serial bus with clock speeds of up to 10
MHz.
The principal synthesizer phase detector drives a low current charge
pump and a high current charge pump simultaneously. Maximum
output current is 0.4 mA with the low current charge pump (pin CPP)
and 3.2 mA with the other (pin CPPF). The auxiliary phase detector
drives only one charge pump. The programmable charge pump
currents are fixed by an external resistance Rext at pin lSET. Only
passive loop filters are necessary.
To reduce crosstalk between different parts of the synthesizer,
separate power supply and ground pins are provided to the
analogue and digital sections.
Each synthesizer can be powered down independently to save
current via software programming or hardwire pins AON / PON.
An on-chip 7 bit DAC allows adjustment of external functions, such
as temperature compensation of the VTCXO, power amplifier
control, etc.
1.2 FEATURES
• Dual frequency synthesizers
• Operating voltage range 2.7 to 5.5 V for battery powered
operation
• Low current consumption, 10 mA typically at 5.5 V (two PLLs
enabled)
• Integrated fully programmable main divider for each synthesizer
– Principal: 512 to 131,071 up to 1.25 GHz input
– Auxiliary: 64 to 16,383 up to 300 MHz input
• Independent fully programmable reference divider for each
synthesizer
– Principal: 8 to 2074 up to 2 MHz output
– Auxiliary: 8 to 2047 up to 1 MHz output
• 3-wire serial bus (Data, Clock, Enable) for fast programming
(fmax = 10 MHz)
• Independent hardwire and software power down modes for both
synthesizers
• Simple passive loop filters
• Charge pump output current under bus control, with reference
current ISET set by an external reference resistor Rext
• Programmable out-of-lock detector
• Integrated D-to-A converter
• Small SSOP-20 package
1995 Oct 10
906 Revision of AN94002
1 page  
Philips Semiconductors
Low power single/dual frequency synthesizers:
UMA1017M/1018M/1019M(AM)/1020M(AM)
Application note
AN95102
www.datasheet4u.com
introducing a delay in the phase detector reset path. This gives
the current sources enough time to respond.
– The second problem is that the charge pump gain is dependent
on temperature and VCO control voltage. In this region, the
gain varies as a function of the phase error. When the phase
error increases outside the defined region, the charge pump
gain becomes essentially independent and constant (see curve
overleaf). This section is intended to show the linearity of the
phase detectors and charge pumps.
Measurement method:
Figure 2–3. Auxiliary Charge Pump (CPA) Output Current
vs Voltage
Figure 2–6. UMA1018M Principal Synthesizer Phase Detector
Linearity Measurement
A frequency generator supplies the reference frequency fXTAL and
the main frequency fPI. These frequencies are divided down to
obtain a comparison frequency of 100 kHz. The generator allows
controlling the phase of the 500 MHz signal with respect to the 10
MHz reference signal. The IAVG phase detector current is measured
as a function of the phase error:
Figure 2–4. Principal Fast Charge Pump Leakage Current vs
Voltage and Temperature
Figure 2–5. Leakage Current of UMA1018M Charge Pumps
vs Voltage
2.1.2 Dynamic Characteristics
Two problems occur when the phase detector input signals’ edges
are very close together, i.e., when the phase error is zero (PLL is
locked) or around zero (PLL has nearly settled after switching).
– The first problem is known as the dead–zone. It is due to the
finite time the current sources take to switch on. The design of
the UMA1018M and UMA1020M takes this into account by
1995 Oct 10
910
5 Page 
Philips Semiconductors
Low power single/dual frequency synthesizers:
UMA1017M/1018M/1019M(AM)/1020M(AM)
Application note
AN95102
Table 2–6. Out-Of-Lock Bit Allocations
OLP
OLA
Out-of-Lock Select
0 0 Output disabled
01
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Auxiliary phase error
Principal phase error
1 1 Both auxiliary and principal
Figure 2–17. Operating Principal of the Out-of-Lock Detector
2.7 Digital-to-Analog Converter
A digital-to-analogue converter is integrated on the UMA1018M and
UMA1020M synthesizers.
The DAC output current is scaled by the external resistance Rext at
pin ISET, also used by the charge pumps. The nominal full scale
current is 2 x ISET. An external user-defined ground referenced
resistance connected to the DAC output allows producing a full
scale voltage (from 0V to VDD1 – 0.4V).
The DAC signal is monotonic across the full range of
programmation. A programmed code of 00 corresponds with the
minimum DAC leakage current (I10min). It should be less than 5 µA
programmed code of 7F corresponds to 2 x ISET x (127 / 128).
The worst monotonic cases occur between 3Fh and 40h, 1Fh and
20h. Here, ∆I measured varies from 0.1 x ∆lexpected to 1.9 x
∆Iexpected.
Example:
Rext = 12k
ISET = 1.2 / 12k = 100 µA
∆lexpected = ISET x 2 x (3Fh – 40h) / 128 = 1.56 µA
° ∆Imeasured can vary between 0.16 µA to 3 µA
The on-board DAC allows adjustment of an external component,
such as the central frequency of a VTCXO (Voltage Controlled
Temperature Compensated Crystal Oscillator).
Figure 3–1. Basic Phase Lock Loop Block Diagram
The correct design of the loop filter is of considerable importance to
have the optimum performance from the synthesizer. The filter
should be designed so as to achieve the required compromise
between noise performance and switching time.
Loop filters are usually passive when used with current charge
pumps, but can be active if desired. Passive loops have the
advantage of reduced noise, fewer parts count and low cost. With
UMA1018M or UMA1020M synthesizers, only passive loop filters
are necessary. Two common configurations are shown overleaf.
The filters in Figure 3–2 are classified in terms of the order of the
loop formed.
With the UMA1018M or UMA1020M, the use of the loop filter (a) is
often sufficient. For applications requiring further comparison
frequency breakthrough rejection, a low pass filter stage (R3, C3)
can be added. It reduces comparison frequency breakthrough spurs
without affecting too much the transient response of the loop when
correctly designed.
3. LOOP FILTER DESIGN
3.1 Basic Loop Filter Design Procedure
This section gives the procedure to ensure a quick and simple loop
filter design. The method is based on first order approximations,
and provides a working solution without the need for computer
simulation. Reading appendices A and B can be useful to clarify
some PLL terms and equations of this chapter.
The purpose of a Phase Locked Loop (PLL) in a single loop
frequency synthesizer as shown in Figure 3–1 is to transfer the
spectral purity and stability of a fixed reference frequency oscillator
(TCXO or VTCXO) to that of the Voltage Controlled Oscillator (VCO)
output.
Figure 3–2. Different Types of Passive Loop Filter
Loop parameters are first chosen, they are:
• VCO frequency fVCO (in Hz)
• Phase comparator frequency fPC (in Hz)
• Switching time tS (in seconds)
• VCO gain KVCO (in Hz/V)
1995 Oct 10
916
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AN95102.PDF ] | |
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