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PDF LTC2274 Data sheet ( Hoja de datos )
| Número de pieza | LTC2274 | |
| Descripción | 105Msps Serial Output ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2274 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
wwwn.daHtasigheheSt4pu.ecoemd Serial Interface (JESD204)
n Sample Rate: 105Msps
n 77.7dBFS Noise Floor
n 100dB SFDR
n SFDR >82dB at 250MHz (1.5VP-P Input Range)
n PGA Front End (2.25VP-P or 1.5VP-P Input Range)
n 700MHz Full Power Bandwidth S/H
n Optional Internal Dither
n Single 3.3V Supply
n Power Dissipation: 1300mW
n Clock Duty Cycle Stabilizer
n Pin Compatible Family
105Msps: LTC2274
80Msps: LTC2273
65Msps: LTC2272
n 40-Pin 6mm × 6mm QFN Package
APPLICATIONS
n Telecommunications
n Receivers
n Cellular Base Stations
n Spectrum Analysis
n Imaging Systems
n ATE
LTC2274
16-Bit, 105Msps Serial
Output ADC
DESCRIPTION
The LTC®2274 is a 105Msps, 16-bit A/D converter with
a high speed serial interface. It is designed for digitizing
high frequency, wide dynamic range signals with an input
bandwidth of 700MHz. The input range of the ADC can
be optimized using the PGA front end. The output data is
serialized according to the JEDEC Serial Interface for Data
Converters specification (JESD204).
The LTC2274 is perfect for demanding applications where
it is desirable to isolate the sensitive analog circuits from
the noisy digital logic. The AC performance includes a
77.7dB Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low internal jitter of 80fs RMS allows under-
sampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±4.5LSB INL
and ±1LSB DNL (no missing codes) over temperature.
The encode clock inputs, ENC+ and ENC–, may be driven
differentially or single-ended with a sine wave, PECL,
LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer
allows high performance at full speed with a wide range
of clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
VCM
2.2μF
1.25V
COMMON MODE
BIAS VOLTAGE
3.3V
SENSE
INTERNAL ADC
REFERENCE
GENERATOR
FAM
8B/10B
ENCODER
16 20
SYNC+
SYNC–
OVDD 1.2V TO 3.3V
0.1μF
AIN +
ANALOG
INPUT
AIN –
CMLOUT+
+
S/H
AMP
–
CLOCK
16-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
CORRECTION
LOGIC
SCRAMBLER/
PATTERN
GENERATOR
SERIALIZER
CMLOUT–
20X
PLL
3.3V
VDD
GND 0.1μF 0.1μF
ENC+ ENC– PGA DITH MSBINV SHDN
PAT1 PAT0 SCRAM SRR1 SRR0
ASIC OR FPGA
50Ω
50Ω
+
SERIAL
RECEIVER
–
2274 TA01
128k Point FFT, fIN = 4.93MHz,
–1dBFS, PGA = 0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10 20 30 40 50
FREQUENCY (MHz)
2274 TA01b
2274f
1
1 page  
LTC2274
COMMON MODE BIAS CHARACTERISTICS The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
wwwV.dCaMtaOsuhtepeutt4Vuo.cltoagme
VCM Output Tempco
VCM Line Regulation
VCM Output Resistance
CONDITIONS
IOUT = 0
IOUT = 0
3.135V ≤ VDD ≤ 3.465V
–1mA ≤ | IOUT | ≤ 1mA
MIN TYP MAX UNITS
1.15 1.25 1.35
V
l 40
ppm/°C
l1
mV/V
l2
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
Encode Inputs (ENC+, ENC–)
CONDITIONS
MIN TYP MAX
VID
Differential Input Voltage
(Note 7)
VICM Common Mode Input Voltage Internally Set
Externally Set (Note 7)
l 0.2
1.6
1.4 3.0
RIN Input Resistance
(See Figure 2)
6
CIN Input Capacitance
SYNC Inputs (SYNC+, SYNC–)
3
VSID SYNC Differential Input
Voltage
(Note 7)
l 0.2
VSICM
SYNC Common Mode Input Internally Set
Voltage
Externally Set (Note 7)
1.6
1.1 2.2
RSIN SYNC Input Resistance
16.5
CSIN SYNC Input Capacitance
3
Logic Inputs (DITH, PGA, MSBINV, SCRAM, FAM, SHDN, SRR1, SRR0, ISMODE, PAT1, PAT0)
VIH
High Level Input Voltage
VDD = 3.3V
VIL
Low Level Input Voltage
VDD = 3.3V
IIN Input Current
VIN = 0V to VDD
CIN Input Capacitance
High-Speed Serial Outputs (CMLOUT+, CMLOUT–)
l2
l
l
0.8
±10
1.5
VOH Output High Level
VOL Output Low Level
VOCM
ROUT
Output Common Mode
Voltage
Output Resistance
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
Directly-Coupled 50Ω to OVDD
Directly-Coupled 100Ω Differential
AC-Coupled
Single-Ended Differential
OVDD
OVDD – 0.2
OVDD – 0.2
OVDD – 0.4
OVDD – 0.6
OVDD – 0.6
OVDD – 0.2
OVDD – 0.4
OVDD – 0.4
l 35 50 65
100
UNITS
V
V
kΩ
pF
V
V
kΩ
pF
V
V
μA
pF
V
V
V
V
V
V
V
V
V
Ω
Ω
2274f
5
5 Page 
LTC2274
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3.3V, OVDD = 1.5V, TA = 25°C, FS = 105Msps,
unless otherwise noted.
www.datasheet4u.com
CMLOUT Dual-Dirac BER
Bathtub Curve, 400Mbps
1.0E+00
1.0E–02
1.0E–04
1.0E–06
1.0E–08
1.0E–10
1.0E–12
1.0E–14
0
0.2 0.4 0.6 0.8 1.0
UNIT INTERVAL (UI)
2274 G26
CMLOUT Dual-Dirac BER
Bathtub Curve, 2.1Gbps
1.0E+00
1.0E–02
1.0E–04
1.0E–06
1.0E–08
1.0E–10
1.0E–12
1.0E–14
0
0.2 0.4 0.6 0.8 1.0
UNIT INTERVAL (UI)
2274 G28
CMLOUT Dual-Dirac BER
Bathtub Curve, 1.2Gbps
1.0E+00
1.0E–02
1.0E–04
1.0E–06
1.0E–08
1.0E–10
1.0E–12
1.0E–14
0
0.2 0.4 0.6 0.8 1.0
UNIT INTERVAL (UI)
2274 G27
CMLOUT Eye Diagram 400Mbps
100mV/DIV
416.7ps/DIV
2274 G29
CMLOUT Eye Diagram 1.2Gbps
CMLOUT Eye Diagram 2.1Gbps
100mV/DIV
138.9ps/DIV
2274 G30
100mV/DIV
79.4ps/DIV
2274 G31
2274f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2274.PDF ] | |
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