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PDF LTC2262-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2262-12 | |
| Descripción | 150Msps Ultralow Power 1.8V ADC | |
| Fabricantes | Linear Dimensions Semiconductor | |
| Logotipo |  |
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FEATURES
www.datasheet4u.com
n 70.5dB SNR
n 88dB SFDR
n Low Power: 146mW
n Single 1.8V Supply
n CMOS, DDR CMOS or DDR LVDS Outputs
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full-Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit and 12-Bit Versions
n 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
Electrical Specifications Subject to Change
LTC2262-12
12-Bit, 150Msps
Ultralow Power 1.8V ADC
DESCRIPTION
The LTC®2262-12 is a sampling 12-bit A/D converter
designed for digitizing high frequency, wide dynamic range
signals. The LTC2262-12 is perfect for demanding commu-
nications applications with AC performance that includes
70.5dB SNRand88dB spuriousfreedynamicrange(SFDR).
Ultralow jitter of 0.17psRMS allows undersampling of IF
frequencies with excellent noise performance.
DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL
(typical) and no missing codes over temperature. The
transition noise is a low 0.3LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
ANALOG
INPUT
+
INPUT
S/H
–
150MHz
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
1.8V
VDD
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
1.2V
TO 1.8V
OVDD
D11
• CMOS
• OR
• LVDS
D0
OGND
GND
226212 TA01a
2-Tone FFT, fIN = 68MHz and 69MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30 40 50 60 70
FREQUENCY (MHz)
226212 TA01b
226212p
1
1 page  
LTC2262-12
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
DIGITAL INPUTS (CS, SDI, SCK)
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VIH High Level Input Voltage
VDD = 1.8V
VIL Low Level Input Voltage
VDD = 1.8V
IIN Input Current
VIN = 0V to 3.6V
CIN Input Capacitance
(Note 8)
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
MIN TYP MAX UNITS
l 1.3
V
l 0.6 V
l –10
10 μA
3 pF
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V
IOH Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT Output Capacitance
(Note 8)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
200 Ω
l –10
10 μA
4 pF
OVDD = 1.8V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.5V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.2V
VOH High Level Output Voltage
VOL Low Level Output Voltage
DIGITAL DATA OUTPUTS (LVDS MODE)
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
l 1.750
l
1.790
0.010
1.488
0.010
1.185
0.010
0.050
V
V
V
V
V
V
VOD Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
l 247
350
454
mV
100Ω Differential Load, 1.75mA Mode
175 mV
VOS Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l 1.125
1.250
1.250
1.375
V
V
RTERM On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100 Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
CMOS Output Modes: Full Data Rate and Double Data Rate
VDD
OVDD
IVDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
IOVDD
PDISS
Digital Supply Current
Power Dissipation
Sine Wave Input, OVDD=1.2V
DC Input
Sine Wave Input, OVDD=1.2V
MIN
l 1.7
l 1.1
l
l
TYP MAX UNITS
1.8 1.9
V
1.9 V
80.9 mA
82.7 mA
5.1 mA
146 mW
155 mW
226212p
5
5 Page 
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2262-12: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
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40 3.5mA LVDS
35
30
25
1.75mA LVDS
20
15
10
1.8V CMOS
5
0 1.2V CMOS
0 25 50 75 100 125 150
SAMPLE RATE (Msps)
226212 G14
LTC2262-12: SNR vs SENSE,
fIN = 5MHz, –1dB
71
70
69
68
67
66
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
SENSE PIN (V)
226212 G15
LTC2262-12
LTC2262-12: SNR vs Sample Rate
and Digital Output Mode,
30MHz Sine Wave Input, –1dB
71
LVDS
CMOS
70
DDR CMOS
69
68
67
0 25 50 75 100 125 150
SAMPLE RATE (Msps)
226212 G18
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
GND (Pin 3): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the VDD of the part and not be driven by a
logic signal.
VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mstaobdieliz(ePrA. RW/hSeEnRC=SVisDlDo)w, C, tShecocnlotcrokldsuthtyeccylcolceksdtaubtyiliczeyrclies
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. When SDI
is low, the part operates normally. When SDI is high, the
226212p
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2262-12.PDF ] | |
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