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ZL30112 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer ZL30112
Beschreibung SLIC/CODEC DPLL
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 18 Seiten
ZL30112 Datasheet, Funktion
ZL30112
SLIC/CODEC DPLL
Data Sheet
Features
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
www.datas1he9e.4t44u.cMomHz input
• Provides 2.048 MHz and 8.192 MHz output clocks
and an 8 kHz framing pulse
• Automatic entry and exit from freerun mode on
reference fail
• Provides DPLL lock and reference fail indication
• DPLL bandwidth of 29 Hz for all rates of input
references
• Less than 0.6 nsecpp intrinsic jitter on all output
clocks
• 20 MHz external master clock source: clock
oscillator or crystal
• Simple hardware control interface
November 2007
Ordering Information
ZL30112LDE1
32 Pin QFN* Tubes, Bake
& Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Synchronizer for POTS SLIC/CODEC
• Rate convert NTR 8 kHz or GPON physical
interface clock to TDM clock
Description
The ZL30112 SLIC/CODEC DPLL contains a digital
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30112 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
Reference
Monitor
State Machine
Master
Clock
REF_FAIL
LOCK
DPLL
Mode
Control
C2o
C8o
F8ko
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.






ZL30112 Datasheet, Funktion
ZL30112
Data Sheet
3.2 Time Interval Error (TIE) Corrector Circuit
The TIE Corrector Circuit eliminates phase transients on the output clock that may occur in the course of recovery
from Automatic Freerun mode to Normal mode.
On recovery from Automatic Freerun mode, the TIE corrector circuit measures the phase delay between the current
phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE
www.dactoarsrheecetto4ru.ccoirmcuit. This circuit creates a new virtual reference signal that is at the same phase position as the
feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it
switches to another reference input or recovers from Automatic Freerun mode.
3.3 Digital Phase Lock Loop (DPLL)
The DPLL of the ZL30112 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled
oscillator as shown in Figure 4. The data path from the phase detector to the filter is tapped and routed to the lock
indicator that provides a lock indication which is output at the LOCK pin.
virtual reference
from
TIE corrector circuit
phase
detector
lock
indicator
LOCK
loop filter
digitally
controlled
oscillator
DPLL reference to
frequency synthesizer
state select from
control state machine
feedback signal from
frequency select MUX
Figure 4 - DPLL Block Diagram
Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the loop filter circuit.
Loop Filter - the loop filter is similar to a first order low pass filter with bandwidth of 29 Hz suitable to provide timing
and synchronization for network interface cards.
6
Zarlink Semiconductor Inc.

6 Page









ZL30112 pdf, datenblatt
ZL30112
Data Sheet
www.datasheet4u.com
ZL30112
OSCi
1 M
20 MHz
OSCo
100
1 µH
The 100 resistor and the 1 µH inductor may improve
stability and are optional.
Figure 7 - Crystal Oscillator Circuit
6.3 Power Up Sequence
The ZL30112 requires that the 3.3 V is not powered after the 1.8 V. This is to prevent the risk of latch-up due to the
presence of parasitic diodes in the IO pads.
Two options are given:
1. Power-up 3.3 V first, 1.8 V later
2. Power up 3.3 V and 1.8 V simultaneously ensuring that the 3.3 V power is never lower than 1.8 V minus a few
hundred millivolts (e.g., by using a schottky diode or controlled slew rate)
6.4 Reset Circuit
A simple power up reset circuit with about a 60 µs reset low time is shown in Figure 8. Resistor RP is for protection
only and limits current into the RST pin during power down conditions. The reset low time is not critical but should
be greater than 300 ns.
ZL30112
+3.3 V
RST
R
10 k
RP
1 k
C
10 nF
Figure 8 - Power-Up Reset Circuit
12
Zarlink Semiconductor Inc.

12 Page





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