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CH5001A Schematic ( PDF Datasheet ) - Chrontel

Teilenummer CH5001A
Beschreibung CMOS COLOR DIGITAL VIDEO CAMERA
Hersteller Chrontel
Logo Chrontel Logo 




Gesamt 30 Seiten
CH5001A Datasheet, Funktion
CH5001A
CHRONTEL
CMOS Color Digital Video Camera
www.daFtaeshaeettu4ur.ceoms
• 352 x 288 active pixel array with color filters, 1/3 inch
lens format ¥
• Programmable formats CIF 352x288, QCIF 176x144,
CCIR601 704x288
• Digital output CCIR601 4:2:2 (8-bit or 16-bit)
• Multidimensional automatic shutter control
• Below 5 LUX sensitivity
• Programmable I2C Serial bus control:
- Frame rate: 30fps-1fps in eight steps
- Gamma correction
- Shutterspeed
- Analog gain
- 16 backlight compensation zones
- Black clamp level
- White balance adjustment
- Power down modes
• Stand-alone 25fps PAL operation with all automatic
features
• Single crystal operation: Video timing on-chip
• Single 5V power supply
• Less than 0.5 watt power dissipation
¥ Patent number x,xxx,xxx patents pending
Description
The CH5001 is a single chip active pixel CMOS color
video camera with digital video output in several formats.
Using sophisticated noise correction circuitry to minimize
fixed pattern noise and dark current effects, the CH5001
provides a supurb quality picture in a low cost device.
The CH5001 uses a proprietary autoshutter algorithm to
dynamically control the shutter time, analog gain, and
black clamp level, providing optimum picture and contrast
under all lighting conditions. The CH5001 also
incorporates extensive on-chip programmable digital
signal processing to maximize the usefulness of the device
in processor driven applications. This includes 16
programmable zones for backlight compensation,
allowing the user to adjust the image to their unique
lighting environment.
Additionally, at power-up the backlight compensation
zone, power-up condition, and direct A/D output modes
are selectable without IIC control by using the PUD pins.
Requiring a minimum of parts for operation, the CH5001
provides a low cost camera for the next generation video
conferencing, videophone, and surveillance products.
Photocell
352
Columns
Array
BG
GR
288
Rows
Row Decode
R
O Shutter
W Control
T
I
M
I
N
G
Color
Control
Gain
A/D
Black
Clamp
Matrix Gamma
Multiply Correct
RGB
to
YCrCB
Filter
Figure 1: Block Diagram
I 2C
BUS
Timing
&
Mode
Control
Output
Format
SD
SC
AS
HREF
PDP*
HS*
VS*
CLKOUT
Reset*
XI/Fin
XO
MONO
TOUT/TOUTB
OVR
Y[7:0]
C[7:0] PUD[6:0]
CRS
201-0000-032 Rev 3.0, 6/2/99
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3






CH5001A Datasheet, Funktion
CHRONTEL
CH5001A
Functional Description
The CH5001 accepts a light input to a photosensitive array, and produces a digital video stream in response.
Each photodiode in the array is covered with a red, green or blue filter whose spectral response is designed to
provide a proper color picture when displayed on a standard monitor/TV. The internal functions performed are:
www.datasheet4uS.ccoamnning of the photodiode array into a serial data stream.
• Programmable gain sample and hold with programmable offset.
• Digitization of data stream.
• Transform the data from the color filter domain to RGB domain.
• Programmable gamma correction and RGB offset.
• Conversion from RGB to YCrCb domain.
• Interpolate/Decimate data to desired resolution
• Formatting of the data stream for the desired type of output.
• Automatic Shutter, Gain and Black Setting.
• Timing signal generation.
• Bus control.
• Power up control of key register bits
Scanning of the photodiode array:
The CH5001 serializes the data captured in the photo array, and outputs one pixel of data each clock period.
The first row is output a programmable number of lines after the leading edge of the vertical sync output. After
the entire row has been output, the next row will be addressed and output. Correlated double sampling tech-
niques are used during readout to reduce fixed pattern noise. After this transfer is complete, pixel data is seri-
ally sent to the programmable gain amplifier and then to an A/D converter.
Programmable gain sample and hold:
The programmable gain is divided into two sections. The first gain block is controlled by PGSH[2:0] and the
second by the ADFS control. ADFS can be treated as the MSB of the gain control, and a plot of gain versus
control setting is shown below. The programmable gain section also provides a bias adjustment, under the con-
trol of the an chip DAC. When the ASBE bit is a one (default) this DAC value is determined automatically, via
a feedback loop which monitors the A/D output signal. When the ASBE bit is a zero, the DAC can be con-
trolled via BCLMP[7:0].
30
25
20
GaindBn 15
10
5
0
0 2 4 6 8 10 12 14 16
Gainn
6 201-0000-032 Rev 3.0, 6/2/99

6 Page









CH5001A pdf, datenblatt
CHRONTEL
CH5001A
Table 4. Register Address Byte (RAB)
B7 B6 B5 B4 B3 B2 B1 B0
X
AutoInc
AR[5]
AR[4]
AR[3]
AR[2]
AR[1]
AR[0]
www.datasheet4u.com
Write: After writing data into a register, the address register will automatically be incremented
by one.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the address register will automatically be incremented by one.
However, for the first read after an RAB, the address register will not be changed.
0: Auto-increment disabled (alternating mode).
Write: After writing data into a register, the address register will remain unchanged until a new
RAB is written.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the address register will remain unchanged.
AR[5:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the address register of the CH5001. The R/W* access, which
follows, is directed to the register specified by the content stored in the address register.
The following two sections describe the operation of the serial interface for the four combinations of R/W* = 0,1
and AutoInc = 0,1.
CH5001 Write Cycle Protocols (R/W* = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the
mastertransmitter. The mastertransmitter releases the SD line (HIGH) during the acknowledge clock pulse. The
slave-receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW
during the HIGH period of the clock pulse. The CH5001 always acknowledges for writes (see Figure 6). Note that
the resultant state on SD is the wired-AND of data outputs from the transmitter and receiver
.
SD Data Output
By Master-Transmitter
SD Data Output
By the CH5001
SC from
Master
Start
Condition
1
not acknowledge
acknowledge
2 89
clock pulse for
acknowledgment
Figure 6: Acknowledge on the Bus
Figure 7 shows two consecutive alternating write cycles for AutoInc = 0 and R/W* = 0. The byte of information
following the Register Address Byte (RAB) is the data to be written into the register specified by AR[5:0]. If
autoInc = 0, then another RAB is expected from the master device followed by another data byte, and so on.
12 201-0000-032 Rev 3.0, 6/2/99

12 Page





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