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S93463 Schematic ( PDF Datasheet ) - Summit Microelectronics

Teilenummer S93463
Beschreibung (S93462 / S93463) Precision Supply-Voltage Monitor and Reset Controller
Hersteller Summit Microelectronics
Logo Summit Microelectronics Logo 




Gesamt 14 Seiten
S93463 Datasheet, Funktion
SUMMIT
MICROELECTRONICS, Inc.
Precision Supply-Voltage Monitor and Reset Controller
S93462/S93463
FEATURES
www.datasPhereetc4uis.cioomn Monitor & RESET Controller
— RESET and RESET Outputs
— Guaranteed RESET Assertion to VCC = 1V
— 150ms Reset Pulse Width
— Internal 1.26V Reference with ±1% Accuracy
— ZERO External Components Required
• Memory
— 1K-bit Microwire Memory
— S93462
– Internally Ties ORG Low
– 100% Compatible With all 8-bit
Implementations
– Sixteen Byte Page Write Capability
— S93463
– Internally Ties ORG High
– 100% Compatible With all 16-bit
Implementations
– Eight Word Page Write Capability
OVERVIEW
The S93462 and S93463 are precision power supervi-
sory circuits providing both active high and active low
reset outputs.
Both devices have 1k-bits of E2PROM memory that is
accessible via the industry standard microwire bus. The
S93462 is configured with an internal ORG pin tied low
providing a 8-bit byte organization and the S93463 is
configured with an internal ORG pin tied high providing
a 16-bit word organization. Both the S93462 and
S93463 have page write capability. The devices are
designed for a minimum 100,000 program/erase cycles
and have data retention in excess of 100 years.
BLOCK DIAGRAM
VCC
8
5kHz
OSCILLATOR
RESET
PULSE
GENERATOR
6 RESET#
CS 1
+ VTRIP
RESET
CONTROL
1.26V
WATCHDOG
TIMER
7 RESET
SK 2
DI 3
MODE
DECODE
ADDRESS
DECODER
WRITE
CONTROL
DO 4
5
GND
DATA I/O
E2PROM
MEMORY
ARRAY
2021 T BD 2.0
© SUMMIT MICROELECTRONICS, Inc. 2001 • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com
Characteristics subject to change without notice
2021 4.2 1/23/01
1






S93463 Datasheet, Funktion
S93462/S93463
SK
www.datasheet4u.com
CS
DI 1 0 0
HIGH-Z
DO
10
STATUS VERIFY
tCS
STANDBY
tSV
BUSY
t EW
READY
t HZ
HIGH-Z
Figure 6. ERAL Instruction Timing
2021 ILL 8 1.0
SK
CS
DI 1 0 0 0 1
DO
DN DO
STATUS VERIFY
tCS
STANDBY
tSV
BUSY
t EW
READY
t HZ
HIGH-Z
Figure 7. WRAL Instruction Timing
2021 ILL 10 1.0
INSTRUCTION SET
Instruction
Start
Bit
READ
1
ERASE
1
WRITE
1
EWEN
1
EWDS
1
ERAL
1
WRAL
1
Opcode
10
11
01
00
00
00
00
Address
x8 x16
A6A0 A5A0
A6A0 A5A0
A6A0 A5A0
11xxxxx 11xxxx
00xxxxx 00xxxx
10xxxxx 10xxxx
01xxxxx 01xxxx
Data
x8
D7D0
D7D0
Comments
x16
Read Address ANA0
Clear Address ANA0
D15D0 Write Address ANA0
Write Enable
Write Disable
Clear All Addresses
D15D0
Write All Addresses
2021 PGM T5 1.1
6
2021 4.2 1/23/01
Summit Microelectronics, Inc.

6 Page









S93463 pdf, datenblatt
S93462/S93463
Ready/Busy Status
During the internal write operation the S93462/463 memory array is inaccessible. After starting the write operation
(taking CS low) the host can implement a 10ms timeout routine or alternatively it can employ a polling routine that tests
www.dathtaeshseteat4teu.coofmthe DO pin.
After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If
it is low the device is still busy with the internal write. If it is high the write operation has completed.
For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then
intermittently test DO. SK is not required for any of these operations. Once the device is ready, it will continue to drive
DO high whenever the S93462/463 is selected. The ready state of DO can be cleared by clocking in a start bit; this
start bit can either be the beginning of a new command sequence or it can be a dummy start bit with CS returning low
before the host issues a new command.
SK
CS
STATUS VERIFY
tCS
DI
tSV tHZ
DO
BUSY READY
HIGH-Z
HIGH-Z
t EW
STATUS CLEARED
2021 ILL 13 1.0
12
2021 4.2 1/23/01
Summit Microelectronics, Inc.

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