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PDF MAX9236 Data sheet ( Hoja de datos )
| Número de pieza | MAX9236 | |
| Descripción | (MAX9234 - MAX9238) DC-Balanced LVDS Deserializers | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
General Description
The MAX9234/MAX9236/MAX9238 deserialize three
LVDS serial-data inputs into 21 single-ended
LVCMOS/LVTTL outputs. A parallel-rate LVDS clock
received with the LVDS data streams provides timing for
deserialization. The outputs have a separate supply,
allowing 1.8V to 5V output logic levels. All these devices
are hot-swappable and allow “on-the-fly” frequency
programming.
The MAX9234/MAX9236/MAX9238 feature DC balance,
which allows isolation between a serializer and deseri-
alizer using AC-coupling. Each deserializer decodes
data transmitted by one of the MAX9209/MAX9211/
MAX9213/MAX9215 serializers.
The MAX9234 has a rising-edge output strobe. The
MAX9236/MAX9238 have a falling-edge output strobe.
The MAX9234/MAX9236/MAX9238 operate in DC-
balanced mode only.
The MAX9234/MAX9236 operate with a parallel input
clock of 8MHz to 34MHz, while the MAX9238 operates
from 16MHz to 66MHz. The transition time of the single-
ended outputs is increased on the low-frequency version
parts (MAX9234/MAX9236) for reduced EMI. The LVDS
inputs meet ISO 10605 ESD specification, ±25kV for Air-
Gap Discharge and ±8kV Contact Discharge.
The MAX9234/MAX9236/MAX9238 are available in 48-pin
TSSOP packages and operate over the -40°C to +85°C
temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
♦ DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦ On-the-Fly Frequency Programming
♦ Operating Frequency Range
8MHz to 34MHz (MAX9234/MAX9236)
16MHz to 66MHz (MAX9238)
♦ Falling-Edge Output Strobe (MAX9236/MAX9238)
♦ Slower Output Transitions for Reduced EMI
(MAX9234/MAX9236)
♦ High-Impedance Outputs when PWRDWN Is Low
Allow Output Busing
♦ 5V-Tolerant PWRDWN Input
♦ PLL Requires No External Components
♦ Up to 1.386Gbps Throughput
♦ Separate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V Logic
♦ LVDS Inputs Meet ISO 10605 ESD Requirements
♦ LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
♦ Low-Profile, 48-Lead TSSOP Package
♦ +3.3V Main Power Supply
♦ -40°C to +85°C Operating Temperature Range
PART
MAX9234EUM
MAX9236EUM
MAX9238EUM
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
48 TSSOP
48 TSSOP
48 TSSOP
PKG
CODE
U48-1
U48-1
U48-1
Functional Diagram and Pin Configuration appear at end of
data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.datasheet4u.com
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Typical Operating Characteristics
(VCC = VCCO = +3.3V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.2V, input common-mode voltage VCM = 1.2V,
TA = +25°C, unless otherwise noted.)
MAX9234/MAX9236
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
90
80
WORST CASE
70
60
27 - 1 PRBS
50
40
30
5
10 15 20 25 30 35 40
FREQUENCY (MHz)
MAX9238
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
180
160
140
WORST CASE
120
100 27 - 1 PRBS
80
60
40
10 20 30 40 50 60 70
FREQUENCY (MHz)
MAX9234/MAX9236
RxOUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
7
6
CLHT
5
4
CHLT
3
2
1
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT SUPPLY VOLTAGE (V)
MAX9238
RxOUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
5
4
CLHT
3
2
CHLT
1
0
2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT SUPPLY VOLTAGE (V)
_______________________________________________________________________________________ 5
5 Page 
www.datasheet4u.com
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1)
where:
C = AC-coupling capacitor (F).
tB = bit time (s).
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
RT = termination resistor (Ω).
RO = output resistance (Ω).
Equation 1 is for two series capacitors (Figure 10). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 11).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x tB x DSV) / (ln (1 - D) x (RT + RO))
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773µF
Jitter due to droop is proportional to the droop and
transition time:
tJ = tT x D (Eq 2)
where:
tJ = jitter (s).
tT = transition time (s) (0 to 100%).
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
tJ = 1ns x 0.02
tJ = 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 11) is:
C = - (4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)
Input Bias and Frequency Detection
The inverting and noninverting LVDS inputs are internally
connected to +1.2V through 42kΩ (min) to provide bias-
ing for AC-coupling (Figure 1). A frequency-detection
circuit on the clock input detects when the input is not
switching, or is switching at low frequency. In this case,
all outputs are driven low. To prevent switching due to
noise when the clock input is not driven, bias the clock
input to differential +15mV by connecting a 10kΩ ±1%
pullup resistor between the noninverting input and VCC,
and a 10kΩ ±1% pulldown resistor between the invert-
ing input and ground. These bias resistors, along with
the 100Ω ±1% tolerance termination resistor, provide
+15mV of differential input.
Unused LVDS Data Inputs
At each unused LVDS data input, pull the inverting input
up to VCC using a 10kΩ resistor, and pull the noninverting
input down to ground using a 10kΩ resistor. Do not con-
nect a termination resistor. The pullup and pulldown resis-
tors drive the corresponding outputs low and prevent
switching due to noise.
PWRDWN
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock-time specification. When the PLL is locking, the
outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
VCC, VCCO, PLL VCC, and LVDS VCC pin with high-fre-
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MAX9236.PDF ] | |
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