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MAX9236 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer MAX9236
Beschreibung (MAX9234 - MAX9238) DC-Balanced LVDS Deserializers
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 15 Seiten
MAX9236 Datasheet, Funktion
www.da19ta-3s6h4e1e;tR4uev.c1o;m10/07
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
General Description
The MAX9234/MAX9236/MAX9238 deserialize three
LVDS serial-data inputs into 21 single-ended
LVCMOS/LVTTL outputs. A parallel-rate LVDS clock
received with the LVDS data streams provides timing for
deserialization. The outputs have a separate supply,
allowing 1.8V to 5V output logic levels. All these devices
are hot-swappable and allow “on-the-fly” frequency
programming.
The MAX9234/MAX9236/MAX9238 feature DC balance,
which allows isolation between a serializer and deseri-
alizer using AC-coupling. Each deserializer decodes
data transmitted by one of the MAX9209/MAX9211/
MAX9213/MAX9215 serializers.
The MAX9234 has a rising-edge output strobe. The
MAX9236/MAX9238 have a falling-edge output strobe.
The MAX9234/MAX9236/MAX9238 operate in DC-
balanced mode only.
The MAX9234/MAX9236 operate with a parallel input
clock of 8MHz to 34MHz, while the MAX9238 operates
from 16MHz to 66MHz. The transition time of the single-
ended outputs is increased on the low-frequency version
parts (MAX9234/MAX9236) for reduced EMI. The LVDS
inputs meet ISO 10605 ESD specification, ±25kV for Air-
Gap Discharge and ±8kV Contact Discharge.
The MAX9234/MAX9236/MAX9238 are available in 48-pin
TSSOP packages and operate over the -40°C to +85°C
temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
On-the-Fly Frequency Programming
Operating Frequency Range
8MHz to 34MHz (MAX9234/MAX9236)
16MHz to 66MHz (MAX9238)
Falling-Edge Output Strobe (MAX9236/MAX9238)
Slower Output Transitions for Reduced EMI
(MAX9234/MAX9236)
High-Impedance Outputs when PWRDWN Is Low
Allow Output Busing
5V-Tolerant PWRDWN Input
PLL Requires No External Components
Up to 1.386Gbps Throughput
Separate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V Logic
LVDS Inputs Meet ISO 10605 ESD Requirements
LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
Low-Profile, 48-Lead TSSOP Package
+3.3V Main Power Supply
-40°C to +85°C Operating Temperature Range
PART
MAX9234EUM
MAX9236EUM
MAX9238EUM
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
48 TSSOP
48 TSSOP
48 TSSOP
PKG
CODE
U48-1
U48-1
U48-1
Functional Diagram and Pin Configuration appear at end of
data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.






MAX9236 Datasheet, Funktion
www.datasheet4u.com
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Pin Description
PIN NAME
FUNCTION
1, 2, 4, 5, 45,
46, 47
RxOUT14–RxOUT20 Channel 2 Single-Ended Outputs
3, 25, 32, 38,
44
6
7, 13, 18
8
9
10
11
GND
N.C.
LVDS GND
RxIN0-
RxIN0+
RxIN1-
RxIN1+
Ground
No Connection
LVDS Ground
Inverting Channel 0 LVDS Serial-Data Input
Noninverting Channel 0 LVDS Serial-Data Input
Inverting Channel 1 LVDS Serial-Data Input
Noninverting Channel 1 LVDS Serial-Data Input
12
14
15
16
17
19, 21
LVDS VCC
RxIN2-
RxIN2+
RxCLK IN-
RxCLK IN+
PLL GND
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to LVDS VCC as possible, with the smallest value capacitor closest to the supply pin.
Inverting Channel 2 LVDS Serial-Data Input
Noninverting Channel 2 LVDS Serial-Data Input
Inverting LVDS Parallel Rate Clock Input
Noninverting LVDS Parallel Rate Clock Input
PLL Ground
20
PLL VCC
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as
close to PLL VCC as possible, with the smallest value capacitor closest to the supply pin.
22
PWRDWN
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are
high impedance when PWRDWN = low or open.
23
RxCLK OUT
Parallel Rate Clock Single-Ended Output. The MAX9234 has a rising-edge strobe. The
MAX9236/MAX9238 have a falling-edge strobe.
24, 26, 27, 29,
30, 31, 33
RxOUT0–RxOUT6 Channel 0 Single-Ended Outputs
28, 36, 48
VCCO
Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to VCCO as possible, with the smallest value capacitor closest to the supply pin.
34, 35, 37, 39,
40, 41, 43
RxOUT7–RxOUT13 Channel 1 Single-Ended Outputs
42
VCC
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close
to VCC as possible, with the smallest value capacitor closest to the supply pin.
6 _______________________________________________________________________________________

6 Page









MAX9236 pdf, datenblatt
www.datasheet4u.com
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
ESD Protection
The MAX9234/MAX9236/MAX9238 ESD tolerance is
rated for IEC 61000-4-2 Human Body Model and ISO
10605 standards. IEC 61000-4-2 and ISO 10605 specifiy
ESD tolerance for electronic systems. The Human Body
Model discharge components are CS = 100pF and RD =
1.5kΩ (Figure 12). For the Human Body Model, all pins
are rated for ±5kV contact discharge. The ISO 10605 dis-
charge components are CS = 330pF and RD = 2kΩ
(Figure 13). For ISO 10605, the LVDS outputs are rated
for ±8kV contact and ±25kV air discharge. The IEC
61000-4-2 discharge components are CS = 150pF and
RD = 330Ω (Figure 14). For IEC 61000-4-2, the LVDS
inputs are rated for ±8kV Contact Discharge and ±15kV
Air-Gap Discharge.
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
VCCO Output Supply and Power Dissipation
The outputs have a separate supply (VCCO) for interfacing
to systems with 1.8V to 5V nominal input-logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for VCCO = 3.6V with 8pF load at several
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for VCCO other than 3.6V with the same
8pF load and worst-case pattern can be calculated using:
II = CTVI 0.5fC x 21 (data outputs)
+ CTVIfC x 1 (clock output)
where:
II = incremental supply current.
CT = total internal (CINT) and external (CL) load capaci-
tance.
VI = incremental supply voltage.
fC = output clock-switching frequency.
R1 R2
1MΩ 1.5kΩ
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
CS
100pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 12. Human Body ESD Test Circuit
R1
50Ω TO 100Ω
R2
2kΩ
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
CS
330pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 13. ISO 10605 Contact Discharge ESD Test Circuit
50Ω TO 100Ω
RD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
CHARGE-CURRENT-
LIMIT RESISTOR
CS
150pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
The incremental current is added to (for VCCO > 3.6V)
or subtracted from (for VCCO < 3.6V) the DC Electrical
Characteristics table maximum supply current. The
internal output buffer capacitance is CINT = 6pF. The
worst-case pattern-switching frequency of the data out-
puts is half the switching frequency of the output clock.
In the following example, the incremental supply current is
calculated for VCCO = 5.5V, fC = 34MHz, and CL = 8pF:
VI = 5.5V - 3.6V = 1.9V
CT = CINT + CL = 6pF + 8pF = 14pF
12 ______________________________________________________________________________________

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