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Teilenummer | UP6161 |
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Beschreibung | Single 12V Input Supply Dual Regulator Synchronous Buck PWM and Linear Regulator Controller | |
Hersteller | UPI | |
Logo | ||
Gesamt 15 Seiten www.datasheet4u.com
Preliminary
uP6161
Single 12V Input Supply Dual Regulator -
Synchronous-Buck-PWM and Linear-Regulator Controller
General Description
Features
The uP6161 integrates a high performance synchronous-
rectified buck controller and a linear-regulator controller.
This part works with a single +12V supply voltage and
delivers two high quality output voltages for both processing
unit and memory unit. An internal linear regulator provides
optimum 9V drive voltage for efficiency and thermal
management.
The buck controller features internal MOSFET drivers that
supports bootstrapped voltage for high efficiency power
conversion. The bootstrap diode is built-in to simplify the
circuit design and minimize external part count. It
incorporates simple, single feedback loop, voltage-control
with fast transient response.
The linear controller drives an external N-Channel MOSFET
with under voltage protection during both soft start and
normal operation.
Other features include adjustable operation frequency,
internal soft start, under voltage protection, adjustable over
current protection and shutdown function. With the above
function, this part provides customers a compact, well
protected and cost-effective solution. This part is available
in SOP-14 and QFN3x3 -16L packages.
Applications
Power Supplies for Microprocessors or
Subsystem Power Supplies
Cable Modems, Set Top Boxes, and DSL
Modems
Industrial Power Supplies; General Purpose
Supplies
12V Input DC-DC Regulators
Low-Voltage Distributed Power Supplies
Operate with Single 12V Supply
Self-Regulated 9V Drive Voltage
Integrated Boot Diode
Provide Two Regulated Voltages
One Synchronous-Rectified Buck Controller
One Linear Controller
Both Controllers Drive N-Channel MOSFETs
Smaller Converter Size
Excellent Output Voltage Regulation
1.5% for Buck Controller
2% for Linear Controller
Simple Single-Loop Control Design
Voltage-Mode PWM Control
Fast Transient Response
High-Bandwidth Error Amplifier
Lossless, Programmable Overcurrent Protection
Uses Lower MOSFET R
DS(ON)
Adjustable Frequency from 150kHz to 1MHz
Internal Soft Start for Both Outputs
Under Voltage Protection for Both Outputs
including Soft Start Cycle
SOP-14 and QFN3x3-16 packages
RoHS Compliant and 100% Lead Free
Ordering Information
Order Number Package Type
Remark
uP6161S14 SOP - 14
uP6161Q
QFN3x3 - 16
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are 100%
matte tin (Sn) plating and suitable for use in SnPb or Pb-
free soldering processes.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
1
www.datasheet4u.com
Preliminary
uP6161
Functional Description
the uP6161 initiates its digital soft start cycle to prevent
surge current from power supply input during turn on
(referring to the Functional Block Diagram). The error
amplifiers are three-input devices. Reference voltage VREF
or the internal soft start voltage SS2/SS3 whichever is
smaller dominates the behavior of the non-inverting inputs
of the error amplifiers. SS2/SS3 internally ramps up to 0.8V
in 4096 cycles of the internal oscillator frequency after the
after the softstart cycle is initiated. Take 600kHz switching
frequency for example (1.67us per cycle), the ramp-up time
is about 6.8ms. Accordingly, the output voltages follow the
soft start signals SS2/SS3 and linearly ramp up to their
final level, resulting minimum inrush current from input
voltage.
The SS2/SS3 signals keep ramping up after it exceeds
the internal 0.8V reference voltages. However, the internal
0.8V reference voltages takes over the behavior of error
amplifier after SS > VREF. When the SS2/SS3 signal climb
to its ceiling voltage (5V), the uP6161 claims the end of
softstart cycle and enable the under voltage protection of
the output voltages.
Figure 3 shows a typical start up interval for uP6161 where
the RT/DIS pin has been released from a grounded (system
shutdown) state. Note the LDO output voltage (LVO)
starts ramping up only after the PWM output voltage
(SVO) is within regulation.
RT/DIS
(1V/Div)
SVO
(0.5V/Div)
LVO
(0.5V/Div)
ramping up to 5VDD. Another softstart is initiated after SS
ramps up to 5VDD. The hiccup period is about 8ms. Figure
4 shows the start up interval where V does not present
IN
initially.
VIN
(5V/Div)
SVO
(0.5V/Div)
LVO
(0.5V/Div)
LGATE
(10V/Div)
Time (5ms/Div)
Figure 4. Softstart where V does not Present Initially.
IN
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the 80% of V supply.
IN
The lower limitation of output voltage is caused by the
internal reference. The upper limitation of the output voltage
is caused by the maximum available duty cycle (80%
typical). This is to leave enough time for overcurrent
detection. Output voltage out of this range is not allowed.
A voltage divider sets the output voltage (refer to the Typical
Application Circuit on page 1 for detail). In real applications,
choose R2 in 100Ω ~ 10kΩ range and choose appropriate
R1 according to the desired output voltage.
VOUT
=
VREF
×
R1+ R2
R2
=
0.8V ×
R1+ R2
R2
PHASE
(10V/Div)
Time (5ms/Div)
Figure 3. Softstart Behavior.
Power Input Detection
The uP6161 detects PHASE voltage for the present of power
input when the UGATE turns on the first time. If the PHASE
voltage does not exceed 2.0V when the UGATE turns on,
the uP6161 asserts that power input in not ready and stops
the softstart cycle. However, the internal SS continues
Overcurrent Protection (OCP)
The uP6161 detects voltage drop across the lower MOSFET
(VPHASE) for overcurrent protection when it is turned on. If
VPHASE is lower than the user-programmable voltage VOCP,
the uP6161 asserts OCP and shuts down the converter.
The OCP level can be calculated according the on-
resistance of the lower MOSFET used.
IOCP
=
− VOCP
RDS(ON)
(A)
Connecting a resistance from LGATE to GND selects the
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
6
6 Page www.datasheet4u.com
Preliminary
uP6161
PVCC9 Voltage vs. VCC12 Voltage
10
9.5
9
8.5
8
7.5
7
8 10 12 14
VCC12 Voltage (V)
PVCC9 Voltage vs. Temperature
9.07
9.06
9.05
9.04
9.03
9.02
9.01
9
-50
0 50 100
Junction Temperature (OC)
VCC12 = 12V
150
Switching Frequency vs. Temperature
2
1
0
-1
-2
-3
-4
-50
0 50 100
Junction Temperature (OC)
150
Typical Operation Characteristics
1000
Switching Frequency vs. RRT
100
10
100
R
RT
(kΩ)
1000
DC/DC Output Voltage vs. Temperature
0.5
0.2
-0.1
-0.4
-0.7
-1
-50
0 50 100
Junction Temperature (OC)
150
LDO Output Voltage vs. Temperature
0.5
0.3
0.1
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
-50 0 50 100 150
Junction Temperature (OC)
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
12
12 Page | ||
Seiten | Gesamt 15 Seiten | |
PDF Download | [ UP6161 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
UP6161 | Single 12V Input Supply Dual Regulator Synchronous Buck PWM and Linear Regulator Controller | UPI |
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