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KT0801 Schematic ( PDF Datasheet ) - KTMicro

Teilenummer KT0801
Beschreibung Monolithic Digital Stereo FM Transmitter Radio Station On A Chip
Hersteller KTMicro
Logo KTMicro Logo 




Gesamt 10 Seiten
KT0801 Datasheet, Funktion
www.datasheet4u.com
Monolithic Digital Stereo FM Transmitter
Radio-Station-on-a-Chip™
KT0801
ƒ Features
Professional Grade System-on-a-Chip (SoC) High-
Fidelity Stereo Audio FM Transmitter:
SNR 68 dB
Stereo Separation > 50dB
International compatible 76MHz ~ 108MHz
Minimal External Component Requirement:
Crystal optional (in lieu of direct feeding
of an external clock)
Ultra-Low Power Consumption:
< 12.6 mA operation current
< 1 µA standby current
Dual Reference Clock Setup:
Supports both 7.6MHz and 15.2MHz
Small Form factor:
24-pin 4x4x0.9 mm QFN (Pb-free and
RoHS Compliant)
Simple Interface:
Single 1.8V (in lieu of 1.6~3.6V regulator
feed)
Industry standard 2-wire I2C MCU
interface compatible
Advanced Digital Audio Signal Processing:
On-chip 20-bit ΔΣ Audio ADC
On-chip DSP core
On-chip 24dB PGA
Automatic calibration against process
and temperature
On-Chip LDO (low-drop-out) regulator:
Accommodates 1.6V ~ 3.6V supply
Programmable transmit level
Programmable pre-emphasis (50/75 µs)
Applications
MP3 Players
Cellular Phones
PDAs
Portable Personal Media player
Laptop Computers
Wireless Speakers
Rev. 1.0
Information furnished by KT Micro is believed to be accurate
and reliable. However, no responsibility is assumed by KT
Micro for its use, nor for any infringements of patents or
other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any
patent or patent rights of KT Micro.
Left In
Right In
KTAT0801 Block Diagram
PGA/ADC
PGA/ADC
Pre-Emph
Pre-Emph
Digital MPX
Xtal1
Xtal2
XTAL
KTM proprietary
Frequency Synthesizer
& FM modulator
SDA
SCL
I2C
Bandgap &
Reference
Channel
Selector
Control
Register
Calibration
RF
Power
Amp
Figure 1: KT0801 System Diagram
RF Out
ƒ General Description
The KT Micro KT0801 Monolithic Digital FM Transmitter
is designed to process high-fidelity stereo audio signal and
transmit modulated FM signal over a short range. The
modulated stereo FM signal can be intercepted and played
back using any FM radio worldwide.
The KT0801 features dual 20-bit ΔΣ audio ADCs, a high-
fidelity digital stereo audio processor and a fully integrated
radio frequency (RF) transmitter. An on-chip low-drop-out
regulator (LDO) allows the chip to be integrated in a wide
range of low-voltage battery-operated systems with power
supply ranging from 1.6V to 3.6V.
The KT0801 is configured as an I2C slave and programmed
through the industry standard 2-wire MCU interface.
Thanks to its high integration level, the KT0801 is mounted
in a generic 24-pin 4x4 QFN package and only requires a
single low-voltage supply and a small-form-factor crystal
(7.6MHz or 15.2MHz) or an external clock to operate.
No external tuning is required that makes design-in effort
minimum.
KT Micro Inc., 30211 Avenida De Las Banderas,
Suite 200, Rancho Santa Margarita, CA 92688
Tel: 949.766.6744
www.ktmicro.com
Fax: 949.766.6745 Copyright ©2006, KT Micro Inc.






KT0801 Datasheet, Funktion
www.datasheet4u.com
KT0801
8-bit
Slave Address & R/W
8-bit
DATA
Start
Condtion
Acknowledge
Acknowledge
Stop
Condtion
Figure 4: Serial Interface Slave Mode Protocol
A START condition is defined as a HIGH to LOW transition on the data line while the SCLK line is held
high. After this has been transmitted by the controller (Master), the bus is considered busy. The next byte of
data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8th bit
tells whether the master is receiving data from the slave or transmitting data to the slave. When ADDR is
set to “0” (i.e. tied to ground), the I2C write address is 0x6C and the read address is 0x6D.
Data transfer with acknowledge is obligatory. The transmitter must release the SDA line during the
acknowledge pulse. The receiver must then pull the SDA line LOW so that it remains stable during the
HIGH period of the acknowledge clock pulse. A receiver that has been addressed is obligated to generate
an acknowledge signal after each byte of data has been received.
ƒ Register Bank
The register bank stores channel frequency codes, calibration parameters, operation status, mode and power
controls, which can be accessed by the internal digital controller, state machines and external micro
controllers through the serial interface.
All registers are 8 bits wide. Control logics are active high unless specifically noted.
CH_SEL0 (Address: 0x00, Default: 0x81)
Bits Type Default Label
Description
7:0 RW 0x81
CHSEL[7:0]
FM Channel Selection[7:0]
CHSEL[10:0] definition : Channel selection code. 0 to 108 MHz with 100 kHz step. 0x000 corresponds to
0Hz; 0x001 corresponds to 100 kHz, and so on.
CH_SEL1 (Address: 0x01, Default: 0x03)
Bits Type Default
7:6 RW 0x0
Label
RFGAIN[1:0]
Description
Transmission Range Adjust
00: Lowest Range
01: Low Range
10: High Range
11: Highest Range
Copyright ©2006, KT Micro, Inc.

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