Datenblatt-pdf.com


92CD54IF Schematic ( PDF Datasheet ) - Toshiba Semiconductor

Teilenummer 92CD54IF
Beschreibung TMP92CD54IF
Hersteller Toshiba Semiconductor
Logo Toshiba Semiconductor Logo 




Gesamt 30 Seiten
92CD54IF Datasheet, Funktion
www.datasheet4u.com
CMOS 32-bit Micro-controller
TMP92CD54IF
TMP92CD54I
1. Outline and Device Characteristics
TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling
equipment which processes mass data.
TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and
various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package.
Device characteristics are as follows:
(1) CPU : 32-bit CPU(900/H1 CPU)
Compatible with TLCS-900,900/L,900/L1,900/H,900/H2’s instruction code
16Mbytes of linear address space
General-purpose register and register banks
Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case)
Minimum instruction execution time : 50ns(at 20MHz)
Internal data bus : 32-bit
(2) Internal memory
Internal RAM : 32K-byte
Internal ROM : 512K-byte Mask ROM
92CD54I-1
2006-01-27






92CD54IF Datasheet, Funktion
www.datasheet4u.com
TMP92CD54I
2.2 Pin names and functions
The following table shows the names and functions of the input/output pins.
Pin name
Pin
number
Number of
pins
In/Out
Function
P00..P07
D0..D7
20th…27th
8
(CMOS)
(TTL)
in/out
in/out
Port 0: I/O port. Input or output specifiable in units of bits.
Data: Data bus 0 to 7.
P40..P47
A0..A7
28th…35th
8
in/out Port4: I/O port. Input or output specifiable in units of bits.
out Address: Address bus 0 to 7.
P70 in/out Port70: I/O port.
RD 81st 1 out Read: Outputs strobe signal to read external memory.
P71
WR
82nd
1
in/out Port 71: I/O port.
out Write: Output strobe signal to write external memory.
P72
SI2
SCL2
P73
CS
83rd
84th
Port 72: I/O port.
1 in/out SBI channel 2: Input data at SIO mode
SBI channel 2: Clock input/output at I²C mode
1
in/out Port 73: I/O port.
out Chip select: Outputs “low” if address is within specified address area.
P74 85th 1 in/out Port 74: I/O port.
P75
WAIT
87th
1
in/out Port 75: I/O port.
in Wait: Signal used to request CPU bus wait.
PC0
TI0
INT1
PC1
TO1
PC2
TO3
INT2
PC3
TI4
INT3
PC4
TO5
PC5
TO7
INT4
PD0
TI8
INT5
A16
WUINT0
58th
57th
56th
55th
54th
53rd
41st
PD1
TI9
INT6
A17
WUINT1
42nd
PD2
TO8
A18
WUINT2
43rd
PD3
TO9
A19
WUINT3
44th
in/out Port C0: I/O port.
1 in Timer input 0: Input pin for timer 0.
INT1
in Interrupt request pin 1: Rising-edge interrupt request pin.
1
in/out Port C1: I/O port.
out Timer output 1: Output pin for timer 1.
in/out Port C2: I/O port.
1 out Timer output 3: Output pin for timer 3.
INT2
in Interrupt request pin 2: Rising-edge interrupt request pin.
in/out Port C3: I/O port.
1 in Timer input 4: Input pin for timer 4.
INT3
in Interrupt request pin 3: Rising-edge interrupt request pin.
1
in/out Port C4: I/O port.
out Timer output 5: Output pin for timer 5.
in/out Port C5: I/O port.
1 out Timer output 7: Output pin for timer 7.
INT4
in Interrupt request pin 4: Rising-edge interrupt request pin.
in/out Port D0: I/O port.
in Timer input 8: Input pin for timer 8.
INT5
in Interrupt request pin 5: Interrupt request pin with programmable rising/falling
1 edge.
WUINT0
out Address: Address bus 16.
in Wake up input 0: Wake up request pin with programmable rising, falling or both
falling and rising edge.
in/out Port D1: I/O port.
in Timer input 9: Input pin for timer 9. INT6
WUINT1
1
in Interrupt request pin 6: Rising-edge interrupt request pin.
out Address: Address bus 17.
in Wake up input 1: Wake up request pin with programmable rising, falling or both
falling and rising edge.
in/out Port D2: I/O port.
out Timer output 8: Output pin for timer 8
1 out Address: Address bus 18.
WUINT2
in Wake up input 2: Wake up request pin with programmable rising, falling or both
falling and rising edge.
in/out Port D3: I/O port.
out Timer output 9: Output pin for timer 9
1 out Address: Address bus 19.
WUINT3
in Wake up input 3: Wake up request pin with programmable rising, falling or both
falling and rising edge.
92CD54I-6
2006-01-27

6 Page









92CD54IF pdf, datenblatt
www.datasheet4u.com
3.3 The Clock Function and Standby Function
3.3.1 Block diagram of system clock
TMP92CD54I
10MHz
X1
X2
High
Frequency
OSC
(10MHz)
Clock doubler*1
(PLL)×4
(40MHz)
To generate the external
memory interface timing
System Clock ‘fc’
1/2
20MHz
CPU
MEMC
INTC
ROMC
PORT
1/2 CAN
10MHz SIO
TIMER
WDT
SBI
A/D
RTC
2/5
(32.768 kHz)
(32.768 kHz)
XT1 Low frequency
XT2 OSC
fs
16MHz
SEI
For RTC
14-stage binary counter
*1) Clock-doubler outputs averaging 40MHz clock because it is corrected in clock unit of High Frequency
OSC output (10MHz) though it has the possibility that the tolerance of 1.46ns at 40MHz (reference
data) is included.
Figure 3.3.1 Block Diagram of System clock
92CD54I-12
2006-01-27

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 92CD54IF Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
92CD54IF TMP92CD54IFToshiba Semiconductor
Toshiba Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche