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WED3EG6417S-D4 Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WED3EG6417S-D4
Beschreibung 128MB - 16Mx64 DDR SDRAM UNBUFFERED
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 7 Seiten
WED3EG6417S-D4 Datasheet, Funktion
Whitewww.datasheet4u.com Electronic Designs
WED3EG6417S-D4
*ADVANCED
128MB - 16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
n Double-data-rate architecture
n Bi-directional data strobes (DQS)
n Differential clock inputs (CK & CK#)
n Programmable Read Latency 2,2.5 (clock)
n Programmable Burst Length (2,4,8)
n Programmable Burst type (sequential & interleave)
n Edge aligned data output, center aligned data
input
n Auto and self refresh
n Serial presence detect
n JEDEC standard 200 pin SO-DIMM package
n Power supply: 2.5V ± 0.25V
The WED3DG6417S is a 16Mx64 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of eight 16Mx8 DDR
SDRAMs in 66 pin TSOP package mounted on a 200
pin FR4 Substrate.
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
* This datasheet describes a product that may or may not be under development
and is subject to change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. # 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WED3EG6417S-D4 Datasheet, Funktion
Whitewww.datasheet4u.com Electronic Designs
WED3EG6417S-D4
*ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE
BANK
1. Typical Case : VCC = 2.5V, T = 25°C
2. Worst Case : VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle.
Iout = 0mA
4. Timing patterns
-DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRCD = 2*tCK, tRAG = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
-DDR266B (133MHz, CL = 2.5): tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAG = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
-DDR266A (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAG = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
IDD7A : OPERATING CURRENT : FOUR
BANK OPERATION
1. Typical Case : VCC = 2.5V, T = 25°C
2. Worst Case : VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
Iout = 0mA
4. Timing patterns
-DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 -
repeat the same timing with random address
changing; 100% of data changing at every burst
-DDR266B (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
-DDR266A (133MHz, CL = 2) : tCK = 7.5ns, CL2 = 2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP,
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. # 0
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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