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WED3C7558M-XBX Schematic ( PDF Datasheet ) - White Electronic Designs

Teilenummer WED3C7558M-XBX
Beschreibung RISC Microprocessor Multichip Package
Hersteller White Electronic Designs
Logo White Electronic Designs Logo 




Gesamt 13 Seiten
WED3C7558M-XBX Datasheet, Funktion
Whitewww.datasheet4u.com Electronic Designs
WED3C7558M-XBX
RISC Microprocessor Multichip Package
OVERVIEW
The WEDC 755/SSRAM multichip package is targeted for
high performance, space sensitive, low power systems and
supports the following power management features: doze,
nap, sleep and dynamic power management.
The WED3C7558M-XBX multichip package consists of:
755 RISC processor
Dedicated 1MB SSRAM L2 cache, configured as
128Kx72
21mmx25mm, 255 Ceramic Ball Grid Array (CBGA)
Core Frequency/L2 Cache Frequency (300MHz/
150MHz, 350MHz/175MHz)
Maximum 60x Bus frequency = 66MHz
The WED3C7558M-XBX is offered in Commercial (0°C
to +70°C), industrial (-40°C to +85°C) and military (-55°C
to +125°C) temperature ranges and is well suited for
embedded applications such as missiles, aerospace,
flight computers, fire control systems and rugged critical
systems.
* This product is subject to change without notice.
FEATURES
Footprint compatible with WED3C750A8M-200BX
Footprint compatible with Motorola MPC 745
FIGURE 1 – MULTI-CHIP PACKAGE DIAGRAM
August 2002
Rev. 7
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com






WED3C7558M-XBX Datasheet, Funktion
Whitewww.datasheet4u.com Electronic Designs
WED3C7558M-XBX
Signal Name
STMS
SYSCLK
TA#
TBEN
TBST#
TCK
TDI (6)
TDO
TEA#
TLBISYNC#
TMS (6)
TRST# (6)
TS#
TSIZ[0-2]
TT[0-4]
WT
VCC (2)
VOLDET (3)
PACKAGE PINOUT LISTING (continued)
Pin Number
Active
B8
C9 —
H14 Low
C2 High
A14 Low
C11 High
A11 High
A12 High
H13 Low
C4 Low
B11 High
C10 Low
J13 Low
A13, D10, B12
High
B13, A15, B16, C14, C15
High
D2 Low
F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9
F3 Low
I/O
Input
Input
Input
Input
I/O
Input
Input
Output
Input
Input
Input
Input
I/O
Output
I/O
Output
Output
2.0V (7) 3.3V (7)
2.0V 2.0V
——
NOTES:
1. These are test signals for factory use only and must be pulled up to OVCC for
normal machine operation.
2. OVCC inputs supply power to the I/O drivers and VCC inputs supply power to the
processor core.
3. Internally tied to GND in the BGA package to indicate to the power supply that a
low-voltage processor is present. This signal is not a power supply pin.
4. To allow processor bus I/0 voltage changes, provide the option to connect BVSEL
and L2VSEL independently to either OVCC (Selects 3.3V Interface) or to GND
(Selects 2.0V Interface).
5. Uses one of 15 existing no-connects in WEDC’s WED3C750A8M-200BX.
6. Internal pull up on die.
7. OVCC supplies power to the processor bus, JTAG, and all control signals except
the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVCC supplies power to the L2
cache I/O interface (L2ADDR (0-16], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT)
and the L2 control signals and the SSRAM power supplies; and VCC supplies power
to the processor core and the PLL and DLL (after filtering to become AVCC and
L2AVCC respectively). These columns serve as a reference for the nominal voltage
supported on a given signal as selected by the BVSEL/L2VSEL pin configurations
and the voltage supplied. For actual recommended value of Vin or supply voltages
see Recommended Operating Conditions.
8. Uses one of 20 existing VCC pins in WEDC's WED3C750A8M-200BX, no board
level design changes are necessary. For new designs of WED3C7558M-XBX refer
to PLL power supply filtering.
9. L20VCC for future designs that will require 2.0V L2 cache power supply - compatible
with existing design using WED3C750A8M-200BX.
10. To disable SSRAM TAP controllers without interfering with the normal operation of
the devices, STCK should be tied low (GND) to prevent clocking the devices.
11. STDI and STMS are internally pulled up and may be left unconnected. Upon
power-up the SSRAM devices will come up in a reset state which will not interfere
with the operation of the device.
August 2002
Rev. 7
6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

6 Page









WED3C7558M-XBX pdf, datenblatt
Whitewww.datasheet4u.com Electronic Designs
WED3C7558M-XBX
PACKAGE DESCRIPTION
Package Outline
Interconnects
Pitch
Maximum module height
Ball diameter
21x25mm
255 (16x16 ball array less one)
1.27mm
3.90mm
0.8mm
PACKAGE DIMENSIONS 255 BALL GRID ARRAY
TOP VIEW
BOTTOM VIEW
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516
NOTES:
1. Dimensions in millimeters and paranthetically in inches.
2. A1 corner is designated with a ball missing the array.
August 2002
Rev. 7
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 Page





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