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PDF SFB60N03L Data sheet ( Hoja de datos )

Número de pieza SFB60N03L
Descripción Logic N-Channel MOSFET
Fabricantes SemiWell Semiconductor 
Logotipo SemiWell Semiconductor Logotipo



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No Preview Available ! SFB60N03L Hoja de datos, Descripción, Manual

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SemiWell Semiconductor
SFB60N03L
Logic N-Channel MOSFET
Features
Low RDS(on) (0.0135)@VGS=10V
Low Gate Charge (Typical 21.5nC)
Low Crss (Typical 130pF)
Improved dv/dt Capability
100% Avalanche Tested
Maximum Junction Temperature Range (175°C)
General Description
This Power MOSFET is produced using SemiWell’s advanced
planar stripe, DMOS technology. This latest technology has been
especially designed to minimize on-state resistance, have a low
gate charge with superior switching performance, and rugged
avalanche characteristics. This Power MOSFET is well suited
for synchronous DC-DC Converters and Power Management in
portable and battery operated products.
Symbol
1. Gate {
{ 2. Drain
◀▲
{ 3. Source
D2-PACK (TO-263)
2
1
3
Absolute Maximum Ratings
Symbol
VDSS
ID
IDM
VGS
EAS
dv/dt
PD
TSTG, TJ
TL
Parameter
Drain to Source Voltage
Continuous Drain Current(@TC = 25°C)
Continuous Drain Current(@TC = 100°C)
Drain Current Pulsed
Gate to Source Voltage
Single Pulsed Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation(@TA = 25 °C) *
Total Power Dissipation(@TC = 25 °C)
Derating Factor above 25 °C
Operating Junction Temperature & Storage Temperature
Maximum Lead Temperature for soldering purpose,
1/8 from Case for 5 seconds.
(Note 1)
(Note 2)
(Note 3)
Value
30
60
43
240
±20
270
7.0
3.75
100
0.67
- 55 ~ 175
300
Thermal Characteristics
Symbol
Parameter
RθJC
Thermal Resistance, Junction-to-Case
RθJA
Thermal Resistance, Junction-to-Ambient *
RθJA
Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended (PCB Mount)
Min.
-
-
-
Value
Typ.
-
-
-
September, 2002. Rev. 0.
Copyright@SemiWell Semiconductor Co., Ltd., All rights reserved.
Max.
1.50
40
62.5
Units
V
A
A
A
V
mJ
V/ns
W
W
W/°C
°C
°C
Units
°C/W
°C/W
°C/W
1/7

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SFB60N03L pdf
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SFB60N03L
Fig. 12. Gate Charge Test Circuit & Waveforms
Same Type
50KΩ
as DUT
12V 200nF
300nF
VGS
5V
Qg
VGS
VDS
Qgs Qgd
DUT
1mA
Fig 13. Switching Time Test Circuit & Waveforms
VDS
5V
Pulse
Generator
RG
RL
VDD
( 0.5 rated VDS )
DUT
VDS
90%
Charge
Vin 10%
td(on)
tr
t on
td(off)
tf
t off
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
10V
VDS
ID
RG
L
VDD
DUT
EAS = --21--
LL IAS2
------B--V--D--S-S-------
BVDSS -- VDD
BVDSS
IAS
ID (t)
VDD
VDS (t)
t p Time
5/7

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