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PDF CY7C1219F Data sheet ( Hoja de datos )
| Número de pieza | CY7C1219F | |
| Descripción | 1-Mbit (32K x 36) Pipelined DCD Sync SRAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1219F
1-Mbit (32K x 36) Pipelined DCD Sync
SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 32K × 36-bit common I/O architecture
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CCoEn1tr)o, ldeinppthu-tesxp(AanDsSioCn,
Chip Enables
ADSP, and
(CE2
ADV),
aWndriCteE3E),naBbulresst
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1219F operates from a +3.3V core power supply
while all outputs operate with a +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
166 MHz 133 MHz
Maximum Access Time
3.5 4.0
Maximum Operating Current
240 225
Maximum CMOS Standby Current
40 40
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05416 Rev. *A
Revised April 10, 2004
1 page  
CY7C1219F
Pwwinw.DDaetasSchreiept4tUio.cnoms (continued)
Pin TQFP
Type
VSSQ
5,10,21,26,
55,60,71,
76
I/O Ground
MODE
31
Input-
Static
NC 14,16,38,39,
42,43,49,50,
66
Ground for the I/O circuitry.
Description
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1219F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Synchronous Chip Selects CE1, CE2, CE3 and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the Write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tCO if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single read cycles are supported.
The CY7C1219F is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will three-state immediately
after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and BW[A:D]
signals. The CY7C1219F provides byte write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because the CY7C1219F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQ are automatically three-stated
whenever a write cycle is detected, regardless of the state of
OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BW[A:D]) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQX is written into the
corresponding address location in the memory core. If a byte
write is conducted, only the selected bytes are written. Bytes
not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1219F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQX inputs. Doing so will three-state the output drivers.
As a safety precaution, DQX are automatically three-stated
Document #: 38-05416 Rev. *A
Page 5 of 15
5 Page 
Swwwwi.tDcahtaiSnhgeeWt4Ua.cvoemforms (continued)
Write Timing[16, 17]
tCYC
CY7C1219F
CLK
ADSP
ADSC
ADDRESS
BWE,
BW[A:D]
GW
CE
ADV
OE
Data in (D)
Data Out (Q)
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1 A2
Byte write signals are ignored for first cycle when
ADSP initiates burst
ADSC extends burst
tADS tADH
A3
tWES tWEH
tCES tCEH
tt
DS DH
High-Z t
D(A1)
OEHZ
tWES tWEH
ADV suspends burst
tADVS tADVH
D(A2)
D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
UNDEFINED
Note:
17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Extended BURST WRITE
Document #: 38-05416 Rev. *A
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7C1219F.PDF ] | |
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