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49LF004 Schematic ( PDF Datasheet ) - AMIC

Teilenummer 49LF004
Beschreibung A49LF004
Hersteller AMIC
Logo AMIC Logo 




Gesamt 30 Seiten
49LF004 Datasheet, Funktion
www.DataSheet4U.com
A49LF004
4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
Document Title
4 Mbit CMOS 3.3 Volt-only Firmware Hub Flash Memory
Revision History
Rev. No.
0.0
0.1
0.2
1.0
History
Initial issue
Add Pb-Free package type
Change Ordering Information
Final version release
Issue Date
November 21, 2003
August 20, 2004
October 21, 2005
December 13, 2005
Remark
Preliminary
Final
(December, 2005, Version 1.0)
AMIC Technology, Corp.






49LF004 Datasheet, Funktion
A49LF004
ABwSwOw.DLaUtaTShEeeMt4UA.cXomIMUM RATINGS*
Temperature Under Bias . . . . . . . .. . . . . . -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . . . . -65°C to + 125°C
D.C. Voltage on Any Pins with Respect to Ground (1)
. . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . -0.5V to VDD + 0.5V
Package Power Dissipation Capability (Ta=25°C)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . -0.5V to VDD + 0.5V
Output Short Circuit Current (2) . . . . . . … . . . . . . . . . 50mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage
transitions, input or I/O pins may undershoot VSS to -2.0V for
periods of up to 20ns. Maximum DC voltage on input and I/O
pins is VDD + 0.5V. During voltage transitions, input or I/O pins
may overshoot to VDD + 2.0V for periods up to 20ns.
2. No more than one output is shorted at a time. Duration of the
short circuit should not be greater than one second.
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to this device. These are stress ratings
only. Functional operation of this device at these or any other
conditions above those indicated in the operational sections of these
specifications are not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may affect device
reliability.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . ….. . . . . . 0°C to +85°C
VDD Supply Voltages
VDD for all devices . . ….. . . . . . . . . . . . . . . . +3.0V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
MODE SELECTION
The A49LF004 flash memory devices can operate in two
distinct interface modes: the Firmware Hub Interface
(FWH) mode and the Address/Address Multiplexed (A/A Mux)
mode. The IC (Interface Configuration pin) is used to set the
interface mode selection. If the IC pin is set to logic High, the
device is in A/A Mux mode; while if the IC pin is set Low, the
device is in the FWH mode. The IC selection pin must be
configured prior to device operation. The IC pin is internally
pulled down if the pin is not connected. In FWH mode, the
device is configured to interface with its host using Intel’s
Firmware Hub proprietary protocol. Communication between
Host and the A49LF004 occurs via the 4-bit I/O
communication signals, FWH [3:0] and the FWH4. In A/A
Mux mode, the device is programmed via an 11-bit address
A10-A0 and an 8-bit data I/O7-I/O0 parallel signals. The
address inputs are multiplexed in row and column selected
by control signal R/C# pin. The column addresses are
mapped to the higher internal addresses, and the row
addresses are mapped to the lower internal
addresses. See the Device Memory Maps in Figure 3 for
address assignment.
FWH MODE OPERATION
The FWH interface consists of four data signals (FWH[3:0]),
one control signal (FWH4) and a clock (CLK). The data
signals, control signal and clock comply with PCI
specifications. Operations such as Memory Read and
Memory Write use Intel FWH propriety protocol. JEDEC
Standard SDP (Software Data Protection) Byte-Program and
Block-Erase command sequences are incorporated into the
FWH memory cycles. Chip-Erase command is only available
in A/A Mux mode. The addresses and data are transferred
through FWH[3:0] synchronized with the input clock CLK
during a FWH memory cycle. The pulse of FWH4 is inserted
for at least one clock period to indicate the start of a FWH
memory cycle. The address or data on FWH[3:0] is latched
on the rising edge of CLK. The device enters standby mode
when FWH4 is high and no internal operation is in progress.
The device is in ready mode when FWH4 is low and no
activity is on the FWH bus.
FWH Read Operation
FWH Read operations read from the memory cells or specific
registers in the FWH device. A valid FWH Read operation
starts when FWH4 is Low as CLK rises and a START value
“1101b” is on FWH[3:0]. Addresses and data are transferred
to and from the device decided by a series of “fields”. Field
sequences and contents are strictly defined for FWH Read
operations. Refer to Table 2 for FWH Read Cycle Definition.
FWH Write Operation
FWH Write operations write to the FWH Interface or FWH
registers. A valid FWH Write operation starts when FWH4 is
Low as CLK rises and a START value “1110b” is on
FWH[3:0]. Addresses and data are transferred to and from
the device decided by a series of “fields”. Field sequences
and contents are strictly defined for FWH Write operations.
Refer to Table 3 for FWH write Cycle Definition.
FWH Abort Operation
If FWH4 is driven low for one or more clock cycles during a
FWH cycle, the cycle will be terminated and the device will
wait for the ABORT command. The host may drive the
FWH[3:0] with ‘1111b’ (ABORT command) to return the
device to Ready mode. If abort occurs during a Write
operation, the data may be incorrectly altered.
Response To Invalid Fields
During FWH operations, the FWH will not explicitly indicate
that it has received invalid field sequences. The response to
specific invalid fields or sequences is as follows:
Address out of range: The FWH address sequence is 7
fields long (28 bits), but only the last five address fields
(20 bits) will be decoded by A49LF004. Address A22 has the
special function of directing reads and writes to the flash
memory (A22=1) or to the register space (A22=0).
(December, 2005, Version 1.0)
5 AMIC Technology, Corp.

6 Page









49LF004 pdf, datenblatt
Tabwleww7.:DAat/aAShMeeutx4UM.coomde Operation Selection
Mode
Read
Write
Standby
Output Disable
Reset
RST#
VIH
VIH
VIH
VIH
VIL
OE#
VIL
VIH
VIH
VIH
X
WE#
VIH
VIL
VIH
X
X
Product Identification
VIH VIL VIH
A49LF004
Address
AIN
AIN
X
X
X
A21 – A2 = X, A1 = VIL, A0 = VIL
A21 – A2 = X, A1 = VIL, A0 = VIH
A21 – A2 = X, A1 = VIH, A0 = VIH
I/O
DOUT
DIN
High Z
High Z
High Z
Manufacturer ID
Device ID
Continuation ID
Block-Erase Operation
The Block-Erase Operation allows the system to erase the
device in 64 KByte uniform block size for the A49LF004. The
Block-Erase operation is initiated by executing a six-byte
command load sequence for Software Data Protection with
Block-Erase command (30H or 50H) and block address. The
internal Block-Erase operation begins after the sixth WE# pulse.
The End-of-Erase can be determined using either Data# Polling
or Toggle Bit methods. See Figure 15 for timing waveforms. Any
commands written during the Block- Erase operation will be
ignored.
Chip-Erase
The A49LF004 device provides a Chip-Erase operation only in
A/A Mux mode, which allows the user to erase the entire
memory array to the ‘1’s state. This is useful when the entire
device must be quickly erased. The Chip-Erase operation is
initiated by executing a six-byte Software Data Protection
command sequence with Chip-Erase command (10H) with
address 5555H in the last byte sequence. The internal Erase
operation begins with the rising edge of the sixth WE#. During
the internal Erase operation, the only valid read is Toggle Bit or
Data# Polling. See Table 8 for the command sequence, Figure
16 for timing diagram, and Figure 21 for the flowchart. Any
commands written during the Chip-Erase operation will be
ignored.
Write Operation Status Detection
The A49LF004 device provides two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (I/O7) and
Toggle Bit (I/O6). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Program
or Erase operation. The actual completion of the nonvolatile
write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system may
possibly get an erroneous result, i.e., valid data may appear to
conflict with either I/O7 or I/O6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two times. If both reads are valid, then the device has
completed the Write cycle, otherwise the rejection is valid.
Data# Polling (I/O7)
When the A49LF004 device is in the internal Program operation,
any attempt to read I/O7 will produce the complement of the true
data. Once the Program operation is completed, I/O7 will
produce true data. Note that even though I/O7 may have valid
data immediately following the completion of an internal Write
operation, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent
successive Read cycles after an interval of 1 µs. During internal
Erase operation, any attempt to read I/O7 will produce a ‘0’.
Once the internal Erase operation is completed, I/O7 will
produce a ‘1’. The Data# Polling is valid after the rising edge of
fourth WE# pulse for Program operation. For Block- or Chip-
Erase, the Data# Polling is valid after the rising edge of sixth
WE# pulse. See Figure 12 for Data# Polling timing diagram.
Proper status will not be given using Data# Polling if the address
is in the invalid range.
Toggle Bit (I/O6)
During the internal Program or Erase operation, any consecutive
attempts to read I/O6 will produce alternating ‘0’s and ‘1’s, i.e.,
toggling between 0 and 1. When the internal Program or Erase
operation is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
rising edge of fourth WE# pulse for Program operation. For
Block- or Chip-Erase, the Toggle Bit is valid after the rising edge
of sixth WE# pulse. See Figure 13 for Toggle Bit timing diagram.
Data Protection
The A49LF004 device provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will not
initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited
when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the
Write operation. This prevents inadvertent writes during power-
up or power-down.
(December, 2005, Version 1.0)
11 AMIC Technology, Corp.

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