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PDF ISL6537A Data sheet ( Hoja de datos )
| Número de pieza | ISL6537A | |
| Descripción | ACPI Regulator/Controller | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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®
Data Sheet
February 9, 2005
ISL6537A
FN9143.3
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply VDDQ during S0/S1 and S3 states. During S0/S1 state,
a fully integrated sink-source regulator generates an accurate
(VDDQ/2) high current VTT voltage without the need for a
negative supply. A buffered version of the VDDQ/2 reference is
www.DataSheperot4vUid.ceodmas VREF. A second PWM controller, which requires
external MOSFET drivers, is available for regulation of the
GMCH Core voltage. An LDO controller is also integrated for
the CPU VTT termination voltage regulation and the DAC.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU VTT termination voltage
is within spec and operational.
All outputs, except VDAC, have undervoltage protection.
The switching regulator also has overvoltage and
overcurrent protection. Thermal shutdown is integrated.
Pinout
ISL6537A (QFN)
TOP VIEW
28 27 26 25 24 23 22
5VSBY 1
21 DRIVE3
S3# 2
P12V 3
GND 4
DDR_VTT 5
GND
29
20 FB3
19 PWM4
18 FB4
17 COMP4
DDR_VTT 6
16 COMP
VDDQ 7
15 FB
8 9 10 11 12 13 14
Features
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR VDDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR VTT
- PWM Regulator for GMCH Core
- LDO Regulator for CPU/GMCH VTT Termination
- LDO Regulator for DAC
• ACPI compliant sleep state control
• Glitch-free Transitions During State Changes
• Integrated VREF Buffer
• VDDQ PWM Controller Drives Low Cost N-Channel
MOSFETs
• 250kHz Constant Frequency Operation
- Both PWM controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
• OCP on the VDDQ Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics cards - GPU and memory supplies
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(°C)
PACKAGE
ISL6537ACR
0 to 70
28 Ld 6x6 QFN
ISL6537ACRZ
(See Note)
0 to 70
28 Ld 6x6 QFN
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
PKG. DWG.
#
L28.6x6
L28.6x6
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6537A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
VTT REGULATOR
Upper Divider Impedance
Lower Divider Impedance
VREF_OUT Buffer Source Current
Maximum VTT Load Current
RU - 2.5 -
RL - 2.5 -
IVREF_OUT
- -2
IVTT_MAX Periodic load applied with 30% duty cycle and -3 - 3
10ms period using ISL6537A_6506EVAL1
evaluation board (see Application Note AN1124)
kΩ
kΩ
mA
A
LINEAR REGULATORS
DC Gain
Guaranteed By Design
- 80 -
dB
www.DataSheGeta4inU.Bcaonmdwidth Product
GBWP
15 - - MHz
Slew Rate
DRIVEn High Output Voltage
SR
DRIVEn Unloaded
-6
9.75 10.0
-
-
V/µs
V
DRIVEn Low Output Voltage
- 0.16 0.50
V
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
VFB = 770mV, VDRIVEn = 0V
VFB = 830mV, VDRIVEn = 10V
- 1.7 2.6 mA
- 1.20 2.00 mA
VTT_GMCH/CPU Rising Threshold
VTT_GMCH/CPU Falling Threshold
PROTECTION
S0
S0
.725 .740 -
- 0.700 0.715
V
V
OCSET Current Source
VTT_DDR Current Limit
VDDQ OV Level
VDDQ UV Level
VTT_DDR OV Level
VTT_DDR UV Level
VGMCH UV Level
VTT_GMCH/CPU UV Level
Thermal Shutdown Limit
IOCSET
By Design
VFB/VREF S0/S3
VFB/VREF S0/S3
VTT/VVREF_IN S0
VTT/VVREF_IN S0
VFB4/VREF S0
VFB2/VREF S0
TSD By Design
18 20 22
-3.3 - 3.3
- 115 -
- 75 -
- 115 -
- 85 -
- 75 -
- 75 -
- 140 -
µA
A
%
%
%
%
%
%
°C
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537A enters a reduced
power mode and draws less than 1mA (ICC_S5) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
P12V (Pin 3)
The VTT regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537A provide the return path
for the VTT LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
5 FN9143.3
5 Page 
ISL6537A
12VATX
P12V
GNDP
5VSBY
ISL6537A
UGATE
PHASE
CBP
5VDUAL
5VSBY
CBP
CIN
Q1 L1
VDDQ
LGATE
COMP
www.DataSheet4U.com
FB
VDDQ(2)
VTT(2)
Q2 COUT1
C2
R2
C1
R1
R4 C3 R3
VDDQ
VTT
COUT2
3.3VATX
PWM4
CIN
Q1
Q2 L2
VGMCH
COMP4
FB4
C6
R6
C5
R5
R8 C7 R7
COUT3
DRIVE2
FB2
R9
R10
Q3
VTT_GMCH/CPU
COUT4
3.3VATX
DRIVE3
FB3
GND PAD
R11
R12
Q3
VDAC
COUT5
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converters
Figure 3 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (LO and CO).
∆ VOSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VDDQ
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2 R2
ZFB VDDQ
ZIN
C3 R3
COMP
R1
- FB
+
ISL6537A
REFERENCE
R4
VDDQ
=
0.8
×
1
+
RR-----14-
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR. The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ∆VOSC.
11 FN9143.3
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ISL6537A.PDF ] | |
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