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PDF LPC2387 Data sheet ( Hoja de datos )
| Número de pieza | LPC2387 | |
| Descripción | Single-chip 16-bit/32-bit microcontrollers | |
| Fabricantes | NXP Semiconductors | |
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LPC2387
Single-chip 16-bit/32-bit microcontrollers; 512 kB flash with
ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 02 — 1 February 2008
Product data sheet
1. General description
www.DataSheet4U.com
The LPC2387 microcontroller is based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with 512 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical
performance in interrupt service routines and DSP algorithms, this increases performance
up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
The LPC2387 is ideal for multi-purpose serial communication applications. It incorporates
a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with 4 kB of
endpoint RAM, four UARTs, two CAN channels, an SPI interface, two Synchronous Serial
Ports (SSP), three I2C interfaces, and an I2S interface. This blend of serial
communications interfaces combined with an on-chip 4 MHz internal oscillator, 64 kB
SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for USB and general purpose use,
together with 2 kB battery powered SRAM makes this device very well suited for
communication gateways and protocol converters. Various 32-bit timers, an improved
10-bit ADC, 10-bit DAC, one PWM unit, a CAN control unit, and up to 70 fast GPIO lines
with up to 12 edge or level sensitive external interrupt pins make this microcontroller
particularly suitable for industrial control and medical systems.
2. Features
I ARM7TDMI-S processor, running at up to 72 MHz.
I 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
I 64 kB of SRAM on the ARM local bus for high performance CPU access.
I 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
I 16 kB SRAM for general purpose DMA use also accessible by USB.
I Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip flash with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
I Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
I General Purpose AHB DMA controller (GPDMA) that can be used with the SSP serial
interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port,
as well as for memory-to-memory transfers.
1 page  
NXP Semiconductors
6. Pinning information
6.1 Pinning
LPC2387
Fast communication chip
www.DataSheet4U.com
1 75
LPC2387FBD100
25 51
Fig 2. LPC2387 pinning LQFP100 package
002aad329
6.2 Pin description
Table 3. Pin description
Symbol
Pin
P0[0] to P0[31]
Type
I/O
P0[0]/RD1/TXD3/ 46[1]
SDA1
P0[1]/TD1/RXD3/ 47[1]
SCL1
P0[2]/TXD0
98[1]
P0[3]/RXD0
99[1]
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
81[1]
I/O
I
O
I/O
I/O
O
I
I/O
I/O
O
I/O
I
I/O
I/O
I
I
Description
Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the Pin Connect
block. Pins 12, 13, 14, and 31 of this port are not available.
P0[0] — General purpose digital input/output pin.
RD1 — CAN1 receiver input.
TXD3 — Transmitter output for UART3.
SDA1 — I2C1 data input/output (this is not an open-drain pin).
P0[1] — General purpose digital input/output pin.
TD1 — CAN1 transmitter output.
RXD3 — Receiver input for UART3.
SCL1 — I2C1 clock input/output (this is not an open-drain pin).
P0[2] — General purpose digital input/output pin.
TXD0 — Transmitter output for UART0.
P0[3] — General purpose digital input/output pin.
RXD0 — Receiver input for UART0.
P0[4] — General purpose digital input/output pin.
I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.
RD2 — CAN2 receiver input.
CAP2[0] — Capture input for Timer 2, channel 0.
LPC2387_2
Product data sheet
Rev. 02 — 1 February 2008
© NXP B.V. 2008. All rights reserved.
5 of 47
5 Page 
NXP Semiconductors
LPC2387
Fast communication chip
Table 3. Pin description …continued
Symbol
Pin Type Description
P2[10]/EINT0
53[6]
I/O P2[10] — General purpose digital input/output pin.
Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over
control of the part after a reset.
I EINT0 — External interrupt 0 input.
P2[11]/EINT1/
MCIDAT1/
www.DataSheeI2t4SUT.cXo_mCLK
52[6]
I/O P2[11] — General purpose digital input/output pin.
I EINT1 — External interrupt 1 input.
O MCIDAT1 — Data line for SD/MMC interface.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I2S-bus specification.
P2[12]/EINT2/
MCIDAT2/
I2STX_WS
51[6]
I/O P2[12] — General purpose digital input/output pin.
I EINT2 — External interrupt 2 input.
O MCIDAT2 — Data line for SD/MMC interface.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the
slave. Corresponds to the signal WS in the I2S-bus specification.
P2[13]/EINT3/
MCIDAT3/
I2STX_SDA
50[6]
I/O P2[13] — General purpose digital input/output pin.
I EINT3 — External interrupt 3 input.
O MCIDAT3 — Data line for SD/MMC interface.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the
receiver. Corresponds to the signal SD in the I2S-bus specification.
P3[0] to P3[31]
I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 3 pins depends upon the pin function selected via the Pin Connect
block. Pins 0 through 24, and 27 through 31 of this port are not available.
P3[25]/MAT0[0]/ 27[1]
PWM1[2]
I/O P3[25] — General purpose digital input/output pin.
O MAT0[0] — Match output for Timer 0, channel 0.
O PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26]/MAT0[1]/ 26[1]
PWM1[3]
I/O P3[26] — General purpose digital input/output pin.
O MAT0[1] — Match output for Timer 0, channel 1.
O PWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31]
I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 4 pins depends upon the pin function selected via the Pin Connect
block. Pins 0 through 27, 30, and 31 of this port are not available.
P4[28]/MAT2[0]/ 82[1]
TXD3
I/O P4[28] — General purpose digital input/output pin.
O MAT2[0] — Match output for Timer 2, channel 0.
O TXD3 — Transmitter output for UART3.
P4[29]/MAT2[1]/ 85[1]
RXD3
I/O P4[29] — General purpose digital input/output pin.
O MAT2[1] — Match output for Timer 2, channel 1.
I RXD3 — Receiver input for UART3.
TDO
1[1] O TDO — Test Data Out for JTAG interface.
TDI 2[1] I TDI — Test Data In for JTAG interface.
TMS
3[1] I TMS — Test Mode Select for JTAG interface.
TRST
4[1] I TRST — Test Reset for JTAG interface.
TCK
5[1] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU
clock (CCLK) for the JTAG interface to operate.
LPC2387_2
Product data sheet
Rev. 02 — 1 February 2008
© NXP B.V. 2008. All rights reserved.
11 of 47
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| PDF Descargar | [ Datasheet LPC2387.PDF ] | |
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