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PDF LTC2704 Data sheet ( Hoja de datos )
| Número de pieza | LTC2704 | |
| Descripción | Voltage Output SoftSpan DACs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ Six Programmable Output Ranges:
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
■ Serial Readback of All On-Chip Registers
www.DataSh■eet14UL.ScoBmINL and DNL Over the Industrial
Temperature Range (LTC2704-14/LTC2704-12)
■ Force/Sense Outputs Enable Remote Sensing
■ Glitch Impulse: < 2nV-sec
■ Outputs Drive ±5mA
■ Pin Compatible 12-, 14- and 16-Bit Parts
■ Power-On and Clear to Zero Volts
■ 44-Lead SSOP Package
U
APPLICATIO S
■ Process Control and Industrial Automation
■ Direct Digital Waveform Generation
■ Software Controlled Gain Adjustment
■ Automated Test Equipment
LTC2704
Quad 12-, 14- and 16-Bit
Voltage Output SoftSpan
DACs with Readback
DESCRIPTIO
The LTC®2704-16/LTC2704-14/LTC2704-12 are serial in-
put, 12-, 14- or 16-bit, voltage output SoftSpan™ DACs
that operate from 3V to 5V logic and ±5V to ±15V analog
supplies. SoftSpan offers six output spans—two unipolar
and four bipolar—fully programmable through the 3-wire
SPI serial interface. INL is accurate to 1LSB (2LSB for the
LTC2704-16). DNL is accurate to 1LSB for all versions.
Readback commands allow verification of any on-chip
register in just one 24- or 32- bit instruction cycle. All other
commands produce a “rolling readback” response from
the LTC2704, dramatically reducing the needed number of
instruction cycles.
A Sleep command allows any combination of DACs to be
powered down. There is also a reset flag and an offset
adjustment pin for each channel.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
SI PLIFIED BLOCK DIAGRA
AGND V+1
32 42
VOSB 40
C1B 39
RFBB 37
OUTB 38
AGNDB 41
VOSA 4
C1A 5
DAC B
RFBA 7
OUTA 6
DAC A
AGNDA 3
33 34
GND VDD
V–
REFM1 REFG1 REF1 REF2 REFG2 REFM2 V+2 1,8,15,22,31,36
44 2 43 24 21 23 25
27 VOSC
28 C1C
DAC C
30 RFBC
29 OUTC
–1 –1
26 AGNDC
19 VOSD
DAC D
18 C1D
16 RFBD
17 OUTD
10 13 11 14 9 35 12
CS/LD SCK SDI CLR LDAC RFLAG SRO
20 AGNDD
2704 BD
LTC2704-16
Integral Nonlinearity (INL)
1.0 V+/V– = ±15V
0.8 VREF = 5V
±10V RANGE
0.6
ALL 4 DACS
0.4 SUPERIMPOSED
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2704 TA01b
2704f
1
1 page  
LTC2704
WU
TI I G CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
t11 LDAC Pulse Width
t12 CLR Low to RFLAG Low
t13 CS/LD High to RFLAG High
SCK Frequency
CLOAD = 10pF (Note 3)
CLOAD = 10pF (Note 3)
50% Duty Cycle (Note 5)
● 15
●
●
●
ns
50 ns
40 ns
40 MHz
VDD = 2.7V to 3.3V
t1 SDI Valid to SCK Setup
t2 SDI Valid to SCK Hold
www.DataShte3et4U.com SCK High Time
t4 SCK Low Time
t5 CS/LD Pulse Width
t6 LSB SCK High to CS/LD High
t7 CS/LD Low to SCK Positive Edge
t8 CS/LD High to SCK Positive Edge
t9 SRO Propagation Delay
t10 CLR Pulse Width
t11 LDAC Pulse Width
t12 CLR Low to RFLAG Low
t13 CS/LD High to RFLAG High
SCK Frequency
CLOAD = 10pF
CLOAD = 10pF
CLOAD = 10pF
50% Duty Cycle (Note 5)
●9
●9
● 15
● 15
● 12
●0
● 12
● 12
●
● 90
● 20
●
●
●
ns
ns
ns
ns
ns
ns
ns
ns
26 ns
ns
ns
70 ns
60 ns
25 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The notation V+ is used to denote both V+1 and V+2 when the same
voltage is applied to both pins.
Note 3: Guaranteed by design, not subject to test.
Note 4: Measured in unipolar 0V to 5V mode.
Note 5: When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay as follows:
( )fMAX
=
⎛
⎝⎜ 2
1
t9 +
tS
⎞
⎠⎟
,
where
ts
is
the
setup
time
of
the
receiving
device.
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2704-16
Integral Nonlinearity (INL)
1.0 V+/V– = ±15V
0.8 VREF = 5V
±10V RANGE
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2704 G01
Differential Nonlinearity (DNL)
1.0 V+/V– = ±15V
0.8 VREF = 5V
±10V RANGE
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152
65535
2704 G02
INL vs VREF
1.0 V+/V– = ±15V
0.8 ±5V RANGE
0.6
0.4
MAX
0.2
MAX
0 MIN
–0.2
MIN
–0.4
–0.6
–0.8
–1.0
–10 –8 –6 –4 –2 0 2 4 6
VREF (V)
8 10
2704 G03
2704f
5
5 Page 
U
OPERATIO
SERIAL INTERFACE
When the CS/LD pin is taken low, the data on the SDI pin
is loaded into the shift register on the rising edge of the
clock signal (SCK pin). The minimum (24-bit wide) load-
ing sequence required for the LTC2704 is a 4-bit com-
mand word (C3 C2 C1 C0), followed by a 4-bit address
word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB
first. Figure 1 shows the SDI input word syntax to use
www.DataShweeht4eUn.cwormiting a code or span. If a 32-bit input sequence is
needed, the first eight bits must be zeros, followed by the
same sequence as for a 24-bit wide input. Figure 2 shows
the input and readback sequences for both 24-bit and
32-bit operations.
When CS/LD is low, the Serial Readback Output (SRO) pin
is an active output. The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted into SDI. For a 24-bit load sequence, the 16
readback bits are shifted out on the falling edges of clocks
8-23, suitable for shifting into a microprocessor on the
rising edges of clocks 9-24. For a 32-bit load sequence,
add 8 to these clock cycle counts; see Figure 2b.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output. At the beginning of a load
sequence, when CS/LD is taken low, SRO outputs a logic
low until the readback data begins.
When the asynchronous load pin, LDAC, is taken low, all
DACs are updated with code and span data (data in B1
buffers is copied into B2 buffers). CS/LD must be high
during this operation. The use of LDAC is functionally
identical to the “Update B1→B2” commands.
The codes for the command word (C3-C0) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-A0).
READBACK
Each DAC has two pairs of double-buffered digital regis-
ters, one pair for DAC code and the other for the output
span (four buffers per DAC). Each double-buffered pair
comprises two registers called buffer 1 (B1) and buffer 2
(B2).
LTC2704
B1 is the holding buffer. When data is shifted into B1 via
a write operation, DAC outputs are not affected. The
contents of B2 can only be changed by copying the
contents of B1 into B2 via an update operation (B1 and B2
can be changed together, see commands 0110-1001 in
Table 1). The contents of B2 (DAC code or DAC span)
directly control the DAC output voltage or the DAC output
range.
Additionally each DAC has one readback register associ-
ated with it. When a readback command is issued to a DAC,
the contents of one of its four buffers is copied into its
readback register and serially shifted out onto the SRO pin.
Figure 2 shows the loading and readback sequences. In
the 16-bit data field (D15-D0 for the LTC2704-16, see
Figure 2a) of any write or update command, the readback
pin (SRO) shifts out the contents of the buffer which was
specified in the preceding command. This “rolling
readback” mode of operation can be used to reduce the
number of operations, since any command can be verified
during succeeding commands with no additional over-
head. Table 1 shows the location (readback pointer) of the
data which will be output from SRO during the next
instruction.
For readback commands, the data is shifted out during the
readback instruction itself (on the 16 falling SCK edges
immediately after the last address bit is shifted in on SDI).
When programming the span of a DAC, the span bits are
the last four bits shifted in; and when checking the span of
a DAC using SRO, the span bits are likewise the last four
bits shifted out. Table 3 shows the span codes.
When span information is read back on SRO, the sleep
status of the addressed DAC is also output. The sleep
status bit, SLP, occurs sequentially just before the four
span bits. The sequence is shown in Figures 2a and 2b. See
Table 4 for SLP codes. Note that SLP is an output bit only;
sleep is programmed by using command code 1110 along
with the desired address. Any update command, including
the use of LDAC, wakes the addressed DAC(s).
2704f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2704.PDF ] | |
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