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PDF M30221 Data sheet ( Hoja de datos )
| Número de pieza | M30221 | |
| Descripción | 16-BIT SINGLE-CHIP MICROCOMPUTER | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
www.DataSheAet4cUc.coormdingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
1 page  
Description
Mitsubishi microcomputers
M30221 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1.1 is performance outline of M30221 group.
Table 1.1.1. Performance outline of M30221 group
Item Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
100ns (f(XIN)=10MHz
Memory
ROM
24 Kbytes
capacity
RAM
1.5 Kbytes
I/O port
P0 to P13 (except P77)
8 bits x 4, 2 bits x 1, 6 bits x 3, 7 bits x 2
5 bits x 1, 4 bits x 3
Input port P77
1 bit x 1
Output port SEG2 to SEG15
2 bits x 7
Multifunction TA0 to TA7
16 bits x 8
timer
TB0 to TB5
16 bits x 6
Real time port outputs
8 bits x 3 lines,6 bits x 1 lines
Serial I/O UART0 , UART2
(UART or clock synchronous) x 2
A-D converter
10 bits x 7 channels
D-A converter
8 bits x 2 channels
DMAC
2 channel(trigger:24 sources)
LCD
COM0 to COM3
4 lines
SEG2 to SEG47
40 lines (26 lines are shared with I/O ports)
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
24 internal and 8 external sources, 4 software sources
Clock generating circuit
2 built-in clock generation circuits
(built-in feedbackresistor, and external ceramic or
quartz oscillator)
Supply voltage
4.0 to 5.5V (f(XIN)=10MHz)
2.7 to 5.5V (f(XIN)=7MHz with software one-wait)
Power consumption
18 mW (Vcc=3.3V, f(XIN)=7MHz with software one-wait)
I/O char-
acteristics
I/O withstand voltage (P0 to P13)
Output current P1 to P9,P13
P0, P10 to P12
5V
5 mA
0.1mA("H" output), 2.5mA("L" output)
Device configuration
CMOS silicon gate
Package
120-pin plastic mold QFP
4
5 Page 
CPU
Mitsubishi microcomputers
M30221 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
10
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| PDF Descargar | [ Datasheet M30221.PDF ] | |
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