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R8A66120FFA Schematic ( PDF Datasheet ) - Renesas Technology

Teilenummer R8A66120FFA
Beschreibung 4M-bit x 2 MULTIPLE FIELD MEMORY
Hersteller Renesas Technology
Logo Renesas Technology Logo 




Gesamt 15 Seiten
R8A66120FFA Datasheet, Funktion
R8A66120FFA
4M-bit x 2 MULTIPLE FIELD MEMORY
RJJ03FXXXREJ03F0161-0170
Rev.1.70
May.16.2008
Description
R8A66120FFA is high-speed field memory with two FIFO (First In First Out) memories of
4M-bit, which uses high-performance silicon gate process technology.
Features
•Total memory Capacity
8Mega-bit
•High speed operation
cycle time
10.0ns(Min.)
output access time 6.0ns(Max.)
•Output hold time
•Supply voltage
1.0ns(Min.)
3.3 ± 0.3V
fmax = 100MHz
www.DataSheet4U.com
•Variable length delay bit
•Synchronous write/read operation
•3 states output
•Package
PLQP0048KB-A (48P6Q-A)
( 48pins 7x7mm body LQFP )
Application
W-CDMA base station, Digital PPC, Digital TV,VTR and so on.
Mode Descriptions
1K-word = 1024-words
1024K-word
4bit bus I/F
4
DA<3:0>
CKA
WRESA
WEA
4
1024K-w
X
4-bit
FIFO
4
DB<3:0>
CKB
WRESB
WEB
4
1024K-w
X
4-bit
FIFO
QA<3:0>
RRESA
REA
QB<3:0>
RRESB
REB
The 2 pieces of 1024K-word x 4-bit
FIFO can be operated completely
independently.
2-system individual input
2-system individual output
Pin Configuration (Top view)
REJ03F0161-0170 Rev.1.70 May.16.2008
page 1 of 14
Outline: PLQP0048KB-A (48P6Q-A)






R8A66120FFA Datasheet, Funktion
R8A66120FFA
Timing Requirements (Ta = 0 ~ 70oC,Vcc = 3.3 + 0.3V, GND = 0V, unless otherwise noted)
Symbol
Parameter
Limits
Min. Typ. Max.
tCK Clock (CK) cycle
10 200
tCKH
CK "H" pulse w idth
4
tCKL
CK "L" pulse w idth
4
tDS Input data setup time to CK
4
tDH Input data hold time to CK
0
tWRESS
Write reset setup time to CK
4
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tRRESS
Write reset hold time to CK
Read reset setup time to CK
0
4
tRRESH
Read reset hold time to CK
0
tWES
Write enable setup time to CK
4
tWEH
Write enable hold time to CK
0
tRES
Read enable setup time to CK
4
tREH
Read enable hold time to CK
0
tr, tf Input pulse rise / fall time
3
Unit
ns
Switching Characteristics (Ta = 0 ~ 70oC, Vcc = 3.3 + 0.3V, GND = 0V, unless otherwise noted)
Symbol
Parameter
Limits
Min. Typ. Max.
Unit
tAC Output access time to CK
6
tOH
tOEN
Output hold time to CK
Output enable time to CK
1
1
ns
6
tODIS
Output disable time to CK
1
6
REJ03F0161-0170 Rev.1.70 May.16.2008
page 6 of 14

6 Page









R8A66120FFA pdf, datenblatt
R8A66120FFA
N-bit Delay 2
(Sliding timings of WRES and RRES at cycles corresponding to delay length)
Reset cycle 0 cycle
1 cycle
2 cycle
n-1 cycle
Reset cycle
n cycle
0 cycle
n+1 cycle
1 cycle
n+2 cycle
2 cycle
n+3 cycle
3 cycle
・・・Write side
・・・Read side
CK
WRES
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RRES
Dn
(0) (1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n
Qn (0) (1) (2) (3)
1048576 256
WE, RE“L”
N-bit Delay 3
(Sliding address by disabling RE for cycles corresponding to delay length)
Reset cycle
0 cycle
1 cycle 2 cycle
n-1 cycle
n cycle
0 cycle
n+1 cycle
1 cycle
n+2 cycle
2 cycle
n+3 cycle ・・・Write side
3 cycle ・・・Read side
CK
WRES
RRES
RE
Dn
Qn
(0)
(1)
(2)
(n-2)
(n-1)
(n)
(n+1)
(n+2)
(n+3)
Delay length n
HIGH-Z
(0) (1) (2) (3)
1048576 n 256
WE=“L”
REJ03F0161-0170 Rev.1.70 May.16.2008
page 12 of 14

12 Page





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