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C8051F041 Schematic ( PDF Datasheet ) - Cygnal

Teilenummer C8051F041
Beschreibung (C8051F040 - C8051F043) Mixed-Signal MCU
Hersteller Cygnal
Logo Cygnal Logo 




Gesamt 30 Seiten
C8051F041 Datasheet, Funktion
PRELIMINARY
C8051F040/1/2/3
Mixed-Signal ISP FLASH MCU Family
ANALOG PERIPHERALS
- 10 or 12-Bit SAR ADC
12-Bit (C8051F040/1) or 10-bit (C8051F042/3) Resolution
± 1 LSB INL, guaranteed no missing codes
Programmable Throughput up to 100 ksps
13 External Inputs; Single-Ended or Differential
SW Programmable High Voltage Difference Amplifier
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data-Dependent Windowed Interrupt Generator
Built-in Temperature Sensor
- 8-bit SAR ADC
Programmable Throughput up to 500 ksps
www.DataSheet4U.com 8 External Inputs, Single-ended or differential
Programmable Amplifier Gain: 4, 2, 1, 0.5
- Two 12-bit DACs
Can Synchronize Outputs to Timers for Jitter-Free Wave-
form Generation
- Three Analog Comparators
Programmable Hysteresis/Response Time
- Voltage Reference
- Precision VDD Monitor/Brown-Out Detector
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
- On-Chip Debug Circuitry Facilitates Full- Speed, Non-
Intrusive In-Circuit/In-System Debugging
- Provides Breakpoints, Single-Stepping, Watchpoints,
Stack Monitor; Inspect/Modify Memory and Registers
- Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
- IEEE1149.1 Compliant Boundary Scan
- Complete Development Kit
HIGH SPEED 8051 µC CORE
- Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
- Up to 25 MIPS Throughput with 25 MHz Clock
- 20 Vectored Interrupt Sources
MEMORY
- 4352 Bytes Internal Data RAM (4k + 256)
- 64k Bytes FLASH; In-System programmable in 512-byte
Sectors
- External 64k Byte Data Memory Interface (programma-
ble multiplexed or non-multiplexed modes)
DIGITAL PERIPHERALS
- 8 Byte-Wide Port I/O (C8051F040/2); 5V tolerant
- 4 Byte-Wide Port I/O (C8051F041/3); 5V tolerant
- Bosch Controller Area Network (CAN 2.0B), Hardware
SMBus™ (I2C™ Compatible), SPI™, and Two UART
Serial Ports Available Concurrently
- Programmable 16-bit Counter/Timer Array with
6 Capture/Compare Modules
- 5 General Purpose 16-bit Counter/Timers
- Dedicated Watch-Dog Timer; Bi-directional Reset Pin
CLOCK SOURCES
- Internal Calibrated Programmable Oscillator: 3 to
24.5 MHz
- External Oscillator: Crystal, RC, C, or Clock
- Real-Time Clock Mode using Timer 2, 3, 4, or PCA
SUPPLY VOLTAGE .......................... 2.7V TO 3.6V
- Multiple Power Saving Sleep and Shutdown Modes
100-Pin TQFP and 64-Pin TQFP Packages Available
Temperature Range: -40°C to +85°C
ANALOG PERIPHERALS
TEMP
SENSOR
PGA
VREF
10/12-bit
100ksps
ADC
HV
DIFF AMP
12-Bit
DAC
12-Bit
DAC
8-bit
PGA 500ksps
ADC
+++
---
VOLTAGE
COMPARATORS
DIGITAL I/O
CAN
2.0B
UART0
Port 0
Port 1
UART1
SMBus
SPI Bus
Port 2
Port 3
PCA
Timer 0
Port 4
Timer 1
Timer 2
Timer 3
Timer 4
Port 5
Port 6
Port 7
64 pin 100 pin
HIGH-SPEED CONTROLLER CORE
8051 CPU
(25MIPS)
20
INTERRUPTS
64KB
ISP FLASH
DEBUG
CIRCUITRY
4352 B
SRAM
JTAG
CLOCK
SANITY
CIRCUIT CONTROL
DS005-1.2MAY03
CYGNAL Integrated Products, Inc. © 2003
Page 1






C8051F041 Datasheet, Funktion
PRELIMINARY
C8051F040/1/2/3
17.2.1. Configuring Ports which are not Pinned Out.......................................................208
17.2.2. Configuring the Output Modes of the Port Pins ..................................................208
17.2.3. Configuring Port Pins as Digital Inputs ...............................................................209
17.2.4. Weak Pull-ups......................................................................................................209
17.2.5. External Memory Interface ..................................................................................209
18. CONTROLLER AREA NETWORK (CAN0) ..................................................................215
18.1.Bosch CAN Controller Operation .................................................................................216
18.1.1. CAN Controller Timing.......................................................................................217
18.1.2. Example Timing Calculation for 1 Mbit/Sec Communication ............................217
18.2.CAN Registers...............................................................................................................220
www.DataSheet4U.com 18.2.1. CAN Controller Protocol Registers .....................................................................220
18.2.2. Message Object Interface Registers.....................................................................220
18.2.3. Message Handler Registers..................................................................................221
18.2.4. CIP-51 MCU Special Function Registers ............................................................221
18.2.5. Using CAN0ADR, CAN0DATH, and CANDATL To Access CAN Registers .221
18.2.6. CAN0ADR Autoincrement Feature.....................................................................221
19. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................227
19.1.Supporting Documents ..................................................................................................228
19.2.SMBus Protocol.............................................................................................................229
19.2.1. Arbitration............................................................................................................229
19.2.2. Clock Low Extension...........................................................................................229
19.2.3. SCL Low Timeout ...............................................................................................230
19.2.4. SCL High (SMBus Free) Timeout.......................................................................230
19.3.SMBus Transfer Modes.................................................................................................231
19.3.1. Master Transmitter Mode ....................................................................................231
19.3.2. Master Receiver Mode.........................................................................................231
19.3.3. Slave Transmitter Mode.......................................................................................232
19.3.4. Slave Receiver Mode ...........................................................................................232
19.4.SMBus Special Function Registers ...............................................................................233
19.4.1. Control Register ...................................................................................................233
19.4.2. Clock Rate Register .............................................................................................235
19.4.3. Data Register........................................................................................................236
19.4.4. Address Register ..................................................................................................236
19.4.5. Status Register .....................................................................................................237
20. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................241
20.1.Signal Descriptions........................................................................................................242
20.1.1. Master Out, Slave In (MOSI) ..............................................................................242
20.1.2. Master In, Slave Out (MISO) ..............................................................................242
20.1.3. Serial Clock (SCK) ..............................................................................................242
20.1.4. Slave Select (NSS)...............................................................................................242
20.2.SPI0 Master Mode Operation........................................................................................243
20.3.SPI0 Slave Mode Operation ..........................................................................................245
20.4.SPI0 Interrupt Sources...................................................................................................245
20.5.Serial Clock Timing ......................................................................................................246
20.6.SPI Special Function Registers .....................................................................................247
Page 4
DS005-1.2MAY03 © 2003 Cygnal Integrated Products, Inc.

6 Page









C8051F041 pdf, datenblatt
PRELIMINARY
C8051F040/1/2/3
Figure 12.13. SP: Stack Pointer .............................................................................................140
Figure 12.14. DPL: Data Pointer Low Byte ..........................................................................140
Figure 12.15. DPH: Data Pointer High Byte .........................................................................140
Figure 12.16. PSW: Program Status Word ............................................................................141
Figure 12.17. ACC: Accumulator..........................................................................................142
Figure 12.18. B: B Register ...................................................................................................142
Table 12.4. Interrupt Summary.............................................................................................144
Figure 12.19. IE: Interrupt Enable .........................................................................................146
Figure 12.20. IP: Interrupt Priority ........................................................................................147
Figure 12.21. EIE1: Extended Interrupt Enable 1 .................................................................148
www.DataSheet4U.com Figure 12.22. EIE2: Extended Interrupt Enable 2 .................................................................149
Figure 12.23. EIP1: Extended Interrupt Priority 1.................................................................150
Figure 12.24. EIP2: Extended Interrupt Priority 2.................................................................151
Figure 12.25. PCON: Power Control.....................................................................................153
13. RESET SOURCES ..............................................................................................................155
Figure 13.1. Reset Sources ....................................................................................................155
Figure 13.2. Reset Timing .....................................................................................................156
Figure 13.3. WDTCN: Watchdog Timer Control Register ...................................................158
Figure 13.4. RSTSRC: Reset Source Register.......................................................................159
Table 13.1. Reset Electrical Characteristics .........................................................................160
14. OSCILLATORS...................................................................................................................161
Figure 14.1. Oscillator Diagram ............................................................................................161
Figure 14.2. OSCICL: Internal Oscillator Calibration Register ............................................162
Figure 14.3. OSCICN: Internal Oscillator Control Register .................................................162
Table 14.1. Internal Oscillator Electrical Characteristics.....................................................163
Figure 14.4. CLKSEL: Oscillator Clock Selection Register .................................................163
Figure 14.5. OSCXCN: External Oscillator Control Register...............................................164
15. FLASH MEMORY ..............................................................................................................167
Table 15.1. FLASH Electrical Characteristics .....................................................................168
Figure 15.1. FLASH Program Memory Map and Security Bytes .........................................169
Figure 15.2. FLACL: FLASH Access Limit .........................................................................170
Figure 15.3. FLSCL: FLASH Memory Control ....................................................................171
Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................172
16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM.......................173
Figure 16.1. EMI0CN: External Memory Interface Control .................................................175
Figure 16.2. EMI0CF: External Memory Configuration .......................................................175
Figure 16.3. Multiplexed Configuration Example.................................................................176
Figure 16.4. Non-multiplexed Configuration Example .........................................................177
Figure 16.5. EMIF Operating Modes.....................................................................................178
Figure 16.6. EMI0TC: External Memory Timing Control ....................................................180
Figure 16.7. Non-multiplexed 16-bit MOVX Timing ...........................................................181
Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing............................182
Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing.................................183
Figure 16.10. Multiplexed 16-bit MOVX Timing .................................................................184
Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing .................................185
Page 10
DS005-1.2MAY03 © 2003 Cygnal Integrated Products, Inc.

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