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TMP19A43FZXBG Schematic ( PDF Datasheet ) - Toshiba Semiconductor

Teilenummer TMP19A43FZXBG
Beschreibung 32-bit RISC Microprocessor
Hersteller Toshiba Semiconductor
Logo Toshiba Semiconductor Logo 




Gesamt 70 Seiten
TMP19A43FZXBG Datasheet, Funktion
www.DataSheet4U.com
32bit TX System RISC
TX19A Family
TMP19A43FD/FZXBG
Rev2.0 2007.Apr.9






TMP19A43FZXBG Datasheet, Funktion
TMP19A43
2. Pin Layout and Pin Functions
This section shows the pin layout of TMP19A43 and describes the names and functions of input and output pins.
2.1 Pin Layout (Top view)
Fig. 2-1 Pin Layout Diagram (P-FBGA193) shows the pin layout of TMP19A43.
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17
C1 C2
C16 C17
www.DataSheet4U.Dco1m D2
D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14
D16 D17
E1 E2
E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14
E16 E17
F1 F2
F4 F5 F6
F13 F14
F16 F17
G1 G2
G4 G5
G13 G14
G16 G17
H1 H2
H4 H5
H13 H14
H16 H17
J1 J2
J4 J5
J13 J14
J16 J17
K1 K2
K4 K5
K13 K14
K16 K17
L1 L2
L4 L5
L13 L14
L16 L17
M1 M2
M4 M5
M13 M14
M16 M17
N1 N2
N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14
N16 N17
P1 P2
P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
P16 P17
R1 R2
R16 R17
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
Fig. 2-1 Pin Layout Diagram (P-FBGA193)
TMP19A43 (rev2.0) 2-1
Pin Layout and Pin Functions

6 Page









TMP19A43FZXBG pdf, datenblatt
TMP19A43
Pin name
PD0
HTXD2
PD1
HRXD2
PD2
HSCLK2
HCTS2
PD3-PD5
www.DataSheet4U.cToBmBOUT-
TBDOUT
PD6
ADTRG
KEY31
PE0-PE7
KEY08-KEY15
PF0,PF2
DREQ0,4
KEY16,KEY18
PF1,PF3
DACK0,4
KEY17,KEY19
PF4-PF7
KEY20-KEY23
TCOUT4-
TCOUT7
PG0-PG7
TPD0-TPD7
PH0-PH7
TPC0-TPC7
TPD0-TPD7
DCLK
EJE
PCST4-0
DINT
TOVR/TSR
TCK
TMS
TDI
TDO
TRST
RESET
X1/X2
XT1/XT2
Table 2-6 Pin Names and Functions (5 of 6)
Number Input or
of pins output
Function
1 Input/output Port D0: Input/output port (with pull-up)
Output
Sending serial data 2 at high speeds: Open drain output pin depending on the program used
1 Input/output Port D1: Input/output port (with pull-up)
Input
Receiving serial data 2 at high speeds
1 Input/output Port D2: Input/output port (with pull-up)
Input/output High-speed serial clock input/output 2
Input
Handshake input pin:
Open drain output pin depending on the program used
3 Input/output Ports D3 to D5: Input/output ports (with pull-up) that allow input/output to be set in units of
bits
Output
16-bit timers B, C and D outputs: Pin for outputting 16-bit timers B, C and D
1 Input/output Port D6: Input/output port (with pull-up) that allows input/output to be set in units of bits
Input
Pin (with Schmitt trigger) for starting A/D trigger or A/D converter from an external source
Input
KEY on wake up input 31: (Dynamic pull up is selectable)
Input with Schmitt trigger with Noise filter
8 Input/output Port E: Input/output port (with pull-up) that allows input/output to be set in units of bits
Input
KEY on wake up input 08 to 15: (Dynamic pull up is selectable)
Input with Schmitt trigger with Noise filter
2 Input/output Port F: Input/output port (with pull-up) that allows input/output to be set in units of bits
Input
DMA request signals 0 and 4: For inputting the request to transfer data by DMA from an
external I/O device to DMAC0 or DMAC4
Input
KEY on wake up input 16 to 19: (Dynamic pull up is selectable)
Input with Schmitt trigger with Noise filter
2 Input/output Port F: Input/output port (with pull-up) that allows input/output to be set in units of bits
Output
DMA acknowledge signals 0 and 4: Signal showing that DREQ0 and DREQ4 have
acknowledged a DMA transfer request
Input
KEY on wake up input 16 to 19: (Dynamic pull up is selectable)
Input with Schmitt trigger with Noise filter
4 Input/output Port F: Input/output port (with pull-up) that allows input/output to be set in units of bits
Input
KEY on wake up input 20 to 23: (Dynamic pull up is selectable)
Input with Schmitt trigger
Output
Outputting 32-bit timer if the result of a comparison is a match with Noise filter
8 Input/output Port G: Input/output port (with pull-up) that allows input/output to be set in units of bits
Output
Outputting trace data from the data access address: Signal for DSU-ICE
8 Input/output Port H: Input/output port (with pull-up) that allows input/output to be set in units of bits
Output
Outputting trace data from the program counter: Signal for DSU-ICE
Output
Outputting trace data from the data access address: Signal for DSU-ICE
1 Output
Debug clock: Signal for DSU-ICE
1 Input
DSU-ICE enable: Signal for DSU-ICE (with Schmitt trigger) (with pull-up) with Noise
filter
4 Output
PC trace status: Signal for DSU-ICE
1 Input
Debug interrupt: Signal for DSU-ICE
(input with Schmitt trigger and pull-up) with Noise filter
1 Output
Outputting the status of PD data overflow status: Signal for DSU-ICE
1 Input
Test clock input: Signal for testing DSU-ICE (with Schmitt trigger and pull-up) with Noise
filter
1 Input
Test mode select input: Signal for testing DSU-ICE (with Schmitt trigger and pull-up)
1 Input
Test data input E: Signal for testing JTAG (with Schmitt trigger and pull-up)
1 Output
Test data output: Signal for testing DSU-ICE
1 Input
Test reset input: Signal for testing DSU-ICE (with Schmitt trigger and pull-down)
with Noise filter
1 Input
Reset: Initializing LSI (with pull-up)
Input with Schmitt trigger with Noise filter
2 Input/output Pin for connecting a high-speed oscillator (X1: Input with Schmitt trigger)
2 Input/output Pin for connecting a low-speed oscillator (XT1: Input with Schmitt trigger)
TMP19A43 (rev2.0) 2-7
Pin Layout and Pin Functions

12 Page





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