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Teilenummer | TB1328FG |
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Beschreibung | Sync Separation and H/V Frequency Counter IC | |
Hersteller | Toshiba Semiconductor | |
Logo | ||
Gesamt 47 Seiten TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB1328FG
TB1328FG
Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1328FG includes Audio and video SW blocks, pre-filters for
AD converter, sync separations and an H/V format detector for TV
signals.
The TB1328FG contributes to a reduction in the proportion of PCB
occupied by LCR filters and to the simplification of designs in analog
interfaces.
www.DataSheet4U.com The TB1328FG is equipped with an I2CBUS interface through
which various functions can be controlled.
Features
AUDIO SW BLOCK
・ Audio (L/R) inputs: 8 channels
・ Audio (L/R) output: 2 channels
LQFP64-P-1010-0.50A
Weight: 0.34 g (typ.)
VIDEO SW BLOCK
・ CVBS inputs
・ Y/C inputs
・ Component video inputs (co-use as RGB inputs)
・ Output: 1 channel (Y/CVBS/G,C/Cb/B,Cr/R)
・ Monitor output
(SY/Y/C/CVBS)
VIDEO BLOCK
・ Gain switching: -3 dB / 0 dB / +3 dB(Output: 1 channel)
・ GCA-Amp for only CVBS: 4 to –6dB,6bit(Output: 1 channel)
・ Bandwidth filter: pre-filter for ADC; 5 to 46 MHz variable(Output: 1 channel)
・ +6dB Amp, No pre-filter (Monitor output)
SYNC SEPARATION BLOCK
・ Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i,
VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60
・ HD/VD input: 1 channel; positive and negative input acceptable
・ HD/VD output: positive and negative output selectable
・ Masking pseudo-sync for copyguard signal
OTHERS
・ Line detector for Japanese D-pin
・ S2, S1, insertion detection for S-pin
・ Horizontal and vertical frequency counter
・ Input signal format detection circuit
・ No-input detection
・ Automatic sync process switching mode
・ Programmable number of video inputs
1 2006-11-13
Pin Assignment
www.DataSheet4U.com
AR3 IN
DC6(LINE1-1)
AL3 IN
Cr1/R1 IN
AR4 IN
Cb1/B1 IN
AL4 IN
Y1/G1 IN
AR5 IN
SY1 IN
AL5 IN
SC1 IN
AR6 IN
CVBS3 IN
AL6 IN
Cr2/r2 IN
TB1328FG
AU Vcc (9V)
AR2 OUT
DC2(S1)
AL2 OUT
V/S GND
SYNC2 IN
SYNC FILTER
VD OUT
HD OUT
V/S Vcc (5V)
Cr/R OUT
AR1 OUT
Cb/B OUT
AL1 OUT
CVBS/Y/G OUT
DC1(S2)
6 2006-11-13
6 Page TB1328FG
Bus Control Functions
Write Mode
Register Name
Function
Preset Value
fc HALF
www.DataSheet4U.com YCbCrOUT
FILPASS
YC MIX
MONITOR OUT
f0 SW
BANDWIDTH
GCA V timing
GCA SW
Switches the frequency of bandwidth limit filters for Cb/Cr
The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y.
0: OFF (same for 3 outputs)
1: ON (1/2 fc for Cb/Cr)
Selects the output form Y/Cb/Cr OUT (pins 2,4,6).
(Y OUT, Cb OUT, Cr OUT)=
0000: Mute (mute, mute, mute)
0001: SY1 (pin 42), SC1 (pin 44), mute
0010: SY2 (pin 60), SC2 (pin 62), mute
0011~0101: Not available
0110: CVBS3 (pin 46), mute, mute
0111: Y1 (pin 40), Cb1 (pin 38), Cr1 (pin 36) (mute, when CbCr PIN1=1)
1000: Y2 (pin 52), Cb2 (pin 50), Cr2 (pin 48) (mute, when CbCr PIN2=1)
1001: Y3 (pin 58), Cb3 (pin 56), Cr3 (pin 54) (mute, when CbCr PIN3=1)
1010: Not available
1011: Cr1(as CVBS) (pin 36), mute, mute(when CbCr PIN1=1)
1100: Cr3(as CVBS) (pin 54), mute, mute(when CbCr PIN3=1)
1101 ~ 1111: Not available
Refer also to Function Descriptions.
Switches the bandwidth limit filter.
0: OFF (filters active)
1: ON (bypass)
Mixes Y with C for MONITOR OUT (pin64).
0: OFF (for CVBS)
1: MIX (Y+C)
Selects the output form MONITOR OUT (pin 64) .
When YC MIX=1, a mixed signal is outputted.
0000: Mute
0001: SY1 (pin 42) (+SC1 (pin 44))
0010: SY2 (pin 60) (+SC2 (pin 62))
0011~0101: Not available
0110: CVBS3 (pin 46) (+Cr2 (pin 48), when CbCr PIN2=1)
0111: Y1 (pin 40) (+Cb1 (pin 38))
1000: Y2 (pin 52) (+Cb2 (pin50))
1001: Y3 (pin 58) (+Cb3 (pin 56))
1010: Not available
1011: Cr1((CVBS) (pin 36),when CbCr PIN1=1 )
1100: Cr3((CVBS) (pin 54) when CbCr PIN3=1 )
1101 ~ 1111: Not available
Refer also to Function Descriptions.
Switches the f0 of bandwidth limit filter for YCbCr(RGB)
0: LOW
1: HIGH
Switches the f0 of bandwidth limit filter for YCbCr(RGB) and CVBS output form
Y/Cb/Cr OUT (pins 2,4,6)
0000000: MIN (low)
1111111: MAX (high)
0: GCA V timing OFF 1:GCA V timing ON
0: GCA OFF
1:GCA ON
GCA Gain
000000: Gain MAX (high)
111111: Gain MIN (low)
NOTE: If GCA SW is GCA OFF, set GCA Gain to minimum.
After setting D7=1(SA:04H,12H,13H,14H) and GCA Gain to MIN(3FH), set D7=0(SA:04H,12H,13H,14H).
OFF
(0)
Mute
(0000)
OFF
(0)
OFF
(0)
Mute
(0000)
LOW
(0)
MIN
(0000000)
0: GCA V timing
OFF
0: GCA OFF
Max
(000000)
12 2006-11-13
12 Page | ||
Seiten | Gesamt 47 Seiten | |
PDF Download | [ TB1328FG Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
TB1328FG | Sync Separation and H/V Frequency Counter IC | Toshiba Semiconductor |
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