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PDF HV20320 Data sheet ( Hoja de datos )
| Número de pieza | HV20320 | |
| Descripción | (HV2xx) Low Charge Injection 8-Channel High Voltage Analog Switches | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HV20320 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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HV220/HV20220/HV20320
Low Charge Injection
8-Channel High Voltage Analog Switches
Features
HVCMOS® technology for high performance
Very low quiescent power dissipation – 10µA
Output on-resistance typically 22 ohms
Low parasitic capacitances
DC to 10MHz analog signal frequency
www.DataShee-t640Ud.cBomtypical output off isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
On-chip shift register, latch and clear logic circuitry
Flexible high voltage supplies
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
General Description
These devices are low charge injection 8-channel high-voltage
analog switch integrated circuits (ICs) intended for use in
applications requiring high voltage switching controlled by low
voltage control signals, such as ultrasound imaging and print-
ers. Input data is shifted into an 8-bit shift register which can
then be retained in an 8-bit latch. To reduce any possible clock
feed-through noise, Latch Enable Bar (LE) should be left high
until all bits are clocked in. Using HVCMOS technology, these
switches combine high voltage bilateral DMOS switches and
low power CMOS logic to provide efficient control of high voltage
analog signals.
These ICs are suitable for various combinations of high voltage
supplies, e.g., VPP/VNN : +50V/–150V, or +100V/–100V.B
Block Diagram
DIN
CLK
LATCHES
D
LE
CL
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
D
LE SW1
CL
D
LE SW2
CL
8-Bit
Shift
Register
D
LE
CL
D
LE
CL
SW3
SW4
D
LE SW5
CL
DOUT
D
LE
CL
SW6
D
LE SW7
CL
VDD LE CL
VNN VPP
1 page  
HV220/HV20220/HV20320
Truth Table
D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L Off
H L L On
L
LL
Off
H
LL
On
L
LL
Off
H
LL
On
L
LL
Off
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H
L
LL
LL
On
Off
H LL
On
L LL
Off
H LL
On
L LL
Off
H LL
On
LLL
Off
HLL
On
XXXXXXXXHL
Hold Previous State
XXXXXXXXXH
All Switches Off
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. DOUT is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Logic Timing Waveforms
DATA
IN
DN+1
50%
DN
50%
DN-1
LE
CLOCK
DATA
OUT
VOUT OFF
(TYP)
ON
50%
t SU
50%
t WLE
t SD
50%
th
t DD
50%
t OFF
90%
50%
t ON
10%
CLR
50%
t WCL
50%
5
5 Page 
28-Lead PLCC Package Outline (PJ)
.048/.042
x 45O
4
D
D1
1 28
26
HV220/HV20220/HV20320
.056/.042
x 45O
.150 MAX
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.075 MAX
Note 1
(Index Area)
E1 E
.020 MAX
3 Places
Top View
A
A1 A2
e
Side View
View B
Base
Plane
Seating
Plane
.020 MIN
b1
b
View B
Note 1:
A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol
A A1 A2
MIN .165 .090 .062
Dimension
(inches)
NOM
.172
.105
-
MAX .180 .120 .083
JEDEC Registration MS-018, Variation AB, Issue A, June, 1993.
Drawings not to scale.
b
.013
-
.021
D
.485
.490
.495
D1
.450
.453
.456
E
.485
.490
.495
E1
.450
.453
.456
e
.050
BSC
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP - HV220_HV20220_HV20320
C073107
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HV20320.PDF ] | |
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