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FL128P Schematic ( PDF Datasheet ) - SPANSION

Teilenummer FL128P
Beschreibung S25FL128P
Hersteller SPANSION
Logo SPANSION Logo 




Gesamt 30 Seiten
FL128P Datasheet, Funktion
S25FL128P
www.DataSheet14U2.c8omMegabit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Bus
Data Sheet (Preliminary)
S25FL128P Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S25FL128P_00
Revision 04
Issue Date July 2, 2007






FL128P Datasheet, Funktion
Data Sheet (Preliminary)
Tables
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Table 5.1
Table 7.1
Table 7.2
Table 8.1
Table 8.2
Table 8.3
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 12.1
Table 13.1
Table 15.1
Table 16.1
Table 17.1
Table 18.1
Table 19.1
S25FL128P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
S25FL128P Protected Area Sizes (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . .13
S25FL128P Protected Area Sizes (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . .13
S25FL128P Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
S25FL128P Sector Address Table (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . .15
S25FL128P Sector Address Table (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . .16
Manufacturer & Device Identification, RDID (9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ_ID Command and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
S25FL128P Status Register (Uniform 256 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
S25FL128P Status Register (Uniform 64 KB sector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power-Up Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
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FL128P pdf, datenblatt
Data Sheet (Preliminary)
7. Device Operations
All Spansion SPI devices (S25FL-P) accept and output data in bytes (8 bits at a time).
7.1
Byte or Page Programming
Programming data requires two commands: Write Enable (WREN), which is one byte, and a Page Program
(PP) sequence, which consists of four bytes plus data. The Page Program sequence accepts from 1 byte up
to 256 consecutive bytes of data (which is the size of one page) to be programmed in one operation.
Programming means that bits can either be left at 0, or programmed from 1 to 0. Changing bits from 0 to 1
requires an erase operation. Before this can be applied, the bytes of the memory need to be first erased to all
1’s (FFh) before any programming.
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Sector Erase / Bulk Erase
The Sector Erase (SE) and Bulk Erase (BE) commands set all the bits in a sector or the entire memory array
to 1. While bits can be individually programmed from a 1 to 0, erasing bits from 0 to 1 must be done on a
sector-wide (SE) or array-wide (BE) level. Before this can be applied, the memory array need to be first
erased to all 1's (FFh) before any programming.
7.3 Monitoring Write Operations Using the Status Register
The host system can determine when a Write Status Register, program, or erase operation is complete by
monitoring the Write in Progress (WIP) bit in the Status Register. The Read from Status Register command
provides the state of the WIP bit.
7.4
7.5
Active Power and Standby Power Modes
The device is enabled and in the Active Power mode when Chip Select (CS#) is Low. When CS# is high, the
device is disabled, but may still be in the Active Power mode until all program, erase, and Write Status
Register operations have completed. The device then goes into the Standby Power mode, and power
consumption drops to ISB. The Deep Power Down (DP) command provides additional data protection against
inadvertent signals. After writing the DP command, the device ignores any further program or erase
commands, and reduces its power consumption to IDP.
Status Register
The Status Register contains the status and control bits that can be read or set by specific commands (see
Table Table 11.6, Command Definitions on page 38):
„ Write In Progress (WIP): Indicates whether the device is performing a Write Status Register, program or
erase operation.
„ Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
„ Block Protect (BP2, BP1, BP0 for uniform 256 KB sector product: BP3, BP2, BP1, BP0 for uniform
64 KB sector product): Non-volatile bits that define memory area to be software-protected against
program and erase commands.
„ Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the WP#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register
(SRWD, BP3, BP2, BP1, BP0) become read-only bits.
7.6 Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
„ The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
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