PDF MCF5328 Data sheet ( Hoja de datos )

Número de pieza	MCF5328
Descripción	(MCF532x) Microprocessor
Fabricantes	Freescale Semiconductor
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No Preview Available ! Freescale Semiconductor Data Sheet: Technical Data MCF532x ColdFire® Microprocessor Data Sheet Features www.DataShee•t4UV.ceorsmion 3 ColdFire variable-length RISC processor core • System debug support • JTAG support for system level board testing • On-chip memories – 16-Kbyte unified write-back cache – 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC, LCD controller, and USB host and OTG) • Power management • Liquid Crystal Display Controller (LCDC) • Embedded Voice-over-IP (VoIP) system solution • SDR/DDR SDRAM Controller • Universal Serial Bus (USB) Host Controller • Universal Serial Bus (USB) On-the-Go (OTG) controller • Synchronous Serial Interface (SSI) • Fast Ethernet Controller (FEC) • Cryptography Hardware Accelerators • FlexCAN Module • Three Universal Asynchronous Receiver Transmitters (UARTs) • I2C Module • Queued Serial Peripheral Interface (QSPI) • Pulse Width Modulation (PWM) module • Real Time Clock • Four 32-bit DMA Timers • Software Watchdog Timer • Four Periodic Interrupt Timers (PITs) • Phase Locked Loop (PLL) • Interrupt Controllers (x2) • DMA Controller • FlexBus (External Interface) • Chip Configuration Module (CCM) • Reset Controller • General Purpose I/O interface Document Number: MCF5329DS Rev. 4, 04/2008 MCF5329 MAPBGA–256 17mm x 17mm MAPBGA–196 15mm x 15mm © Freescale Semiconductor, Inc., 2008. All rights reserved. 1 page Hardware Design Considerations 3 Hardware Design Considerations 3.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 2 should be connected between the board VDD and the PLLVDD pins. The resistor and capacitors should be placed as close to the dedicated PLLVDD pin as possible. Board IVDD 10 Ω PLL VDD Pin 10 µF 0.1 µF www.DataSheet4U.com GND Figure 2. System PLL VDD Power Filter 3.2 USB Power Filtering To minimize noise, external filters are required for each of the USB power pins. The filter shown in Figure 3 should be connected between the board EVDD or IVDD and each of the USBVDD pins. The resistor and capacitors should be placed as close to the dedicated USBVDD pin as possible. Board EVDD 0Ω USB VDD Pin 10 µF 0.1 µF GND Figure 3. USB VDD Power Filter NOTE In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown. 3.3 Supply Voltage Sequencing and Separation Cautions The relationship between SDVDD and EVDD is non-critical during power-up and power-down sequences. SDVDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 3.3.1 Power Up Sequence If EVDD/SDVDD are powered up with IVDD at 0 V, the sense circuits in the I/O pads cause all pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD, SDVDD, or PLLVDD by more than 0.4 V during power ramp-up or there is Freescale Semiconductor MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4 5 5 Page Pin Assignments and Reset States Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO Alternate 1 Alternate 2 MCF5327 196 MAPBGA MCF5328 256 MAPBGA MCF53281 MCF5329 256 MAPBGA QSPI QSPI_CS2 PQSPI5 U2RTS — O EVDD P10 T12 T12 QSPI_CS1 PQSPI4 PWM7 USBOTG_ O EVDD L11 T13 T13 PU_EN QSPI_CS0 PQSPI3 PWM5 — O EVDD — P11 P11 www.DataSheet4U.coQmSPI_CLK PQSPI2 I2C_SCL2 — O EVDD N10 R12 R12 QSPI_DIN PQSPI1 U2CTS — I EVDD L10 N12 N12 QSPI_DOUT PQSPI0 I2C_SDA — O EVDD M10 P12 P12 UARTs U1CTS PUARTL7 SSI_BCLK — I EVDD C9 D11 D11 U1RTS PUARTL6 SSI_FS — O EVDD D9 E10 E10 U1TXD PUARTL5 SSI_TXD2 — O EVDD A9 E11 E11 U1RXD PUARTL4 SSI_RXD2 — I EVDD A10 E12 E12 U0CTS PUARTL3 — — I EVDD P13 R15 R15 U0RTS PUARTL2 — — O EVDD N12 T15 T15 U0TXD PUARTL1 — — O EVDD P12 T14 T14 U0RXD PUARTL0 — — I EVDD P11 R14 R14 Note: The UART2 signals are multiplexed on the QSPI, SSI, DMA Timers, and I2C pins. DMA Timers DT3IN DT2IN DT1IN DT0IN JTAG_EN7 DSCLK PSTCLK BKPT DSI DSO DDATA[3:0] PTIMER3 PTIMER2 PTIMER1 PTIMER0 — — — — — — — DT3OUT DT2OUT DT1OUT DT0OUT — TRST2 TCLK2 TMS2 TDI2 TDO — U2RXD I U2TXD I DACK1 DREQ02 I I BDM/JTAG6 —I —I —O —I —I —O —O EVDD C1 F1 F1 EVDD B1 E1 E1 EVDD A1 E2 E2 EVDD C2 E3 E3 EVDD L12 M13 M13 EVDD N14 P15 P15 EVDD L7 T9 T9 EVDD M12 R16 R16 EVDD K12 N14 N14 EVDD N9 N11 N11 EVDD N7, P7, L8, N9, P9, N10, N9, P9, N10, M8 P10 P10 Freescale Semiconductor MCF532x ColdFire® Microprocessor Data Sheet, Rev. 4 11 11 Page

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