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AD7280 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7280
Beschreibung Lithium Ion Battery Monitoring System
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD7280 Datasheet, Funktion
Preliminary Technical Data
FEATURES
12-bit ADC, 1us per channel conversion time
6 Analog Input Channels, CM range 0.5V to 27.5V
6 Temperature Measurements Inputs.
On Chip Voltage Regulator
Cell Balancing Interface
Daisy Chain Interface
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Low Quiescent Current
High Input Impedance
Serial Interface with Alert Function
1 SPI interface for up to 300 channels
On Chip Registers for Channel Sequencing
VDD Operating Range 7.5V to 30V
Temperature Range -40 oC to 105oC
48 lead LQFP and LFCSP Packages
APPLICATIONS
Lithium Ion Battery Monitoring
Nickel Metal Hydride Battery Monitoring
GENERAL DESCRIPTION
The AD72801 contains all the functions required for general
purpose monitoring of stacked Lithium Ion batteries as used in
Hybrid Electric Vehicles. The part has multiplexed analog input
and temperature measurement channels for up to six cells of
battery management. An internal 3-ppm reference is provided
to drive the ADC. The ADC resolution is 12 bits with a 1 Msps
throughput rate offering a 1µs conversion time.
The AD7280 operates from just one VDD supply which has a
range of 7.5V to 30V (with an absolute max rating of 33V). The
part provides 6 pseudo differential analog input channels to
accommodate large common mode signals across the full VDD
range. Each channel allows an input signal range, Vin(+) --
Vin(-), of 0V to 5V. The input pins assume a series stack of 6
cells. In addition the part can accommodate 6 external sensors
for temperature measurement.
The AD7280 includes on chip registers which allow a sequence
of channel measurements to be programmed to suit the
applications requirements.
Lithium Ion Battery
Monitoring System
AD7280
FUNCTIONAL BLOCK DIAGRAM
VDD
Vin(6)
Vin(5)
Vin(4)
Vin(3)
Vin(2)
Vin(1)
Vin(0)
AD7280
MUX
VT(6)
VT(5)
VT(4)
VT(3)
VT(2)
VT(1)
VT TERM
VREF
CREF
REFGND
DAIS Y CHAIN
INTER FACE
++
--
CLOCK
2.5V
REF
CB1
CB6
CEL L
BALANCING
INTER FACE
REGUL ATOR
12 BIT ADC
CONTRO L LOGIC
& SELF TEST
LIMIT REG
SQN LOGIC
DATA MEMO RY
SPI INTER FACE
VREG
DGND
DVCC
AVCC
VDRIVE
SCLK
S D IN
SDOUT
ALERT
CS
PD
CNVST
MASTER
Figure 1
The AD7280 also includes an Alert function which generates an
interrupt output signal if the cell voltages exceed an upper or
lower limit defined by the user. The AD7280 has balancing
interface outputs designed to control external FET transistors to
allow discharging of individual cells.
The AD7280 includes a Built In Self Test feature which
internally applies a known voltage to the ADC inputs.
There is a daisy chain interface which allows up to 50 parts to
be stacked without the need for individual device isolation.
The AD7280 requires only one supply pin which takes 7mA
under normal operation, while converting at 1 Msps.
All this functionality is provided in a 48 pin LQFP or 48 pin
LFCSP package operating over a temperature range of −40°C to
+105°C.
1 Patents Pending
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.






AD7280 Datasheet, Funktion
AD7280
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
Preliminary Technical Data
48 47 46 45 44 43 42 41 40 39 38 37
VIN6 1
CB6 2
VIN5 3
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VIN4 5
CB4 6
VIN3 7
CB3 8
VIN2 9
CB2 10
VIN1 11
CB1 12
PIN 1
AD7280
TOP VIEW
36 VT3
35 VT4
34 VT5
33 VT6
32 VTTERM
31 AGND
30 AVCC
29 VDRIVE
28 ALERTlo
27 ALERT
26 SDO
25 SDOlo
13 14 15 16 17 18 19 20 21 22 23 24
VIN6 1
CB6 2
VIN5 3
CB5 4
VIN4 5
CB4 6
VIN3 7
CB3 8
VIN2 9
CB2 10
VIN1 11
CB1 12
PIN 1
INDICATOR
AD7280
TOP VIEW
36 VT3
35 VT4
34 VT5
33 VT6
32 VTTERM
31 AGND
30 AVCC
29 VDRIVE
28 ALERTlo
27 ALERT
26 SDO
25 SDOlo
Figure 2.
Figure 3.
Table 4.
Pin No.
1, 3, 5, 7,
9, 11, 13
2, 4, 6, 8,
10, 12
14
15
16
17
18
19
Mnemonic
Vin6 to
Vin0
CB6 to CB1
MASTER
PD
VDD
VSS
VREG
DVCC
Description
Analog Input 0 to Analog Input 6. Analog input 0 should be connected to the base of the series connected
battery cells. Analog Input 1 should be connected to the top of cell 1, Analog Input 2 should be connected to
the top of cell 2, etc. The Analog Inputs are multiplexed into the on-chip track-and-hold allowing the potential
across each cell to be measured.
Cell Balance Outputs. These provide a voltage output which can be used to supply the gate drives of a cell
balancing transistor network. Each CB(n) output provides a 5V voltage output referenced to the absolute
voltage of Cell(n-1).
Voltage Input. In an application with 2 or more AD7280s Daisy Chained the MASTER pin of the AD7280
connected directly to the DSP or uP should be connected to the VDD supply pin through a 10kOhm resistor. The
MASTER pin on the remaining AD7280s in the application should be tied to their respective VSS supply pins
through 10kOhm resistors.
Power down Input. This input is used to power down the AD7280. When acting as master the PD input is
supplied from the DSP/uP. When acting as a slave on the Daisy Chain the PD input should be connected to the
PDhi output of the AD7280 immediately below it in potential in the Daisy Chain. This input can also be tied to
VCC and the power down initiated through the serial interface.
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure
AD7280. The supply must be greater than a minimum voltage of 7.5 V. In an application monitoring the cell
voltages of up to 6 series connected battery cells the supply voltage may be supplied directly from the cell with
the highest potential. The maximum voltage which can be applied between VDD and VSS is 30V. Place 10 µF and
100 nF decoupling capacitors on the VDD pin.
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7280. This input should be at the same potential as the AGND voltage.
Analog Voltage output, 5V. The internally generated VREG voltage, which provides the supply voltage for the
ADC core, is available on this pin for use external to the AD7280. Place 10 µF and 100 nF decoupling capacitors
on the VREG pin.
Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.
For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the
voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled
to DGND. Place 100 nF decoupling capacitors on the DVCC pin. The DVCC supply pin should be connected to the
VREG output
Rev. PrD | Page 6 of 33

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AD7280 pdf, datenblatt
AD7280
TYPICAL CONNECTION DIAGRAMS
The AD7280 can be used to monitor 6 battery cells connected
Preliminary Technical Data
in series. A typical configuration for a 6 cell battery monitoring
application is shown in Figure 10.
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0.1µF
10µF
10k
Vin6
CB6
Vin5
CB5
Vin4
CB4
Vin3
VDD MASTER
VREG
DVCC
AVCC
VDRIVE
VREF
CREF
AD7280
10uF
0.1uF
0.1uF
10uF
0.1uF
OPTIONAL
INTERFACE
PINS
CB3
Vin2
CB2
Vin1
CB1
Vin0 VSS
ALERT
CNVST
PD
SDO
SCLK
SDI
CS
Figure 10. AD7280 Configuration Diagram for 6 Battery Cells
µC/µP
4 WIRE SPI
INTERFACE
Lithium Ion Battery applications require a significant number
application.
of individual cells to provide the required output voltage.
Individual AD7280s can monitor the cell voltages and
temperatures of 6 series connected cells. The Daisy Chain
Interface of the AD7280 allows each individual AD7280 to
communicate with another AD7280 immediately above or
below it. The daisy chain interface allows the AD7280s to be
When using a chain of AD7280s it is also recommended that a
100kOhm series resistor be placed on the PD input. This is
recommended to limit current into the PD pin in the event that
the uP/DSP or isolators are connected before the supplies of the
master AD7280.
electrically connected to the battery management chip, as
Please refer to the Daisy Chain Interface Section for a more
shown in Figure 11 without the need for individual isolation
detailed description of the Daisy Chain Interface.
between each AD7280.
Daisy Chain Connection Diagram
In an application which includes a safety mechanism, designed
to open circuit the Battery Stack, additional isolation will be
As shown in Figure 11 external diodes have been included on
required between the AD7280 above the break point and the
the VDD supply to each AD7280 and on each Daisy Chain signal
battery management chip.
between adjacent AD7280’s. These diodes, in combination with
the 10kseries resistors on the analog inputs, are
recommended to prevent damage to the AD7280 in the event of
an open circuit in the battery stack.
EMC Considerations
In addition to the standard decoupling capacitors, C2n and C3n,
as shown in Figure 11, it is also recommended that an option for
additional capacitors, C1n and C4n, be included in the circuit to
It is also recommended that a zener diode be placed across the
increase immunity to Electomagnetic Interference. These
supplies of each AD7280 as shown in Figure 11. This will
capacitors, placed on either side of the VDD protection diode,
prevent an over voltage across the supplies of each AD7280
would be used to decouple the VDD supply of each AD7280 with
during the initial connection of the daisychain of AD7280s to
respect to system ground., that is the ground of the master
the battery stack. A voltage rating of 33V is suggested for this
AD7280 in the daisychain.
zener diode but lower values may also be used to suit the
Rev. PrD | Page 12 of 33

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