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PDF MB90F568 Data sheet ( Hoja de datos )
| Número de pieza | MB90F568 | |
| Descripción | (MB90F56x) 16-bit Proprietary Microcontrollers | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13715-3E
16-bit Proprietary Microcontrollers
CMOS
F2MC-16LX MB90560/565 Series
MB90561/561A/562/562A/F562/F562B/V560
www.DataSheet4U.com
MB90567/568/F568
s DESCRIPTION
The MB90560/565 series is a general-purpose 16-bit microcontroller designed for industrial, OA, and process
control applications that require high-speed real-time processing. The device features a multi-function timer able
to output a programmable waveform.
The microcontroller instruction set is based on the same AT architecture as the F2MC-8L and F2MC-16L families
with additional instructions for high-level languages, extended addressing modes, enhanced signed multiplication
and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a
32-bit accumulator for processing long word (32-bit) data.
s FEATURES
• Clock
• Internal oscillator circuit and PLL clock multiplication circuit
• Oscillation clock
Clock speed selectable from either the machine clock, main clock, or PLL clock. The main clock is the oscillation
clock divided into 2 (0.5 MHz to 8 MHz for a 1 MHz to 16 MHz base oscillation) . The PLL clock is the oscillation
clock multiplied by one to four (4 MHz to 16 MHz for a 4 MHz base oscillation) .
• Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = × 4, VCC = 5.0 V)
• Maximum CPU memory space : 16 MB
• 24-bit addressing
• Bank addressing
s PACKAGES
(Continued)
64-pin plastic QFP
64-pin plastic LQFP
64-pin plastic SH-DIP
(FPT-64P-M06)
(FPT-64P-M09)
(DIP-64P-M01)
1 page  
MB90560/565 Series
2. MB90565 Series
Part Number
MB90F568
Classification
Internal flash memory product
MB90568
MB90567
Internal mask ROM product
ROM size
128 Kbytes
96 Kbytes
RAM size
Dedicated emula-
tor power supply*
4 Kbytes
4 Kbytes
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CPU functions
Number of instructions : 351
Minimum instruction execution time : 62.5 ns for a 4 MHz oscillation (with ×4 multiplier)
Addressing modes : 23 modes
Program patch function : 2 address pointers
Maximum memory space : 16 Mbytes
Ports
UART
I/O ports (CMOS) : 51
Full-duplex, double-buffered
Clock synchronous or asynchronous operation selectable
Can be used as I/O serial
Internal dedicated baud rate generator
2 channels
16-bit reload timer
16-bit reload timer operation
2 channels
Multi-function
timer
16-bit free-run timer × 1 channel
Output compare × 6 channels
Input capture × 4 channels
8/16-bit PPG timer (8-bit × 6 channels or 16-bit × 3 channels)
Waveform generator (8-bit timer × 3 channels) 3-phase waveform output, deadtime output
8/10-bit A/D
converter
8 channels (multiplexed input)
8-bit or 10-bit resolution selectable
Conversion time : 6.13 µs (min.) (for maximum machine clock speed 16 MHz)
DTP/external
interrupts
8 channels (8 channels available, shared with A/D input)
Interrupt triggers :
“L” → “H” edge, “H” → “L” edge, “L” level, “H” level (selectable)
Low power con-
sumption modes
Sleep mode, timebase timer mode, stop mode, and CPU intermittent operation mode
Process
CMOS
Operating voltage 3.3 V ± 0.3 V
* : DIP switch setting (S2) when using the emulation pod (MB2145-507) .
Refer to “2.7 Dedicated Emulator Power Supply” in the “MB2145-507 Hardware Manual” for details.
5
5 Page 
MB90560/565 Series
Pin No.
QFPM06 LQFPM09
SDIP
Pin
Name
Cir- State/
cuit Function
Type* at Reset
Description
P30 to
P35
I/O ports
51 to 56
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50 to 55 58 to 63 RTO0
to
RTO5
E
Event output pins for the output compare and wave-
form generator output pins. The pins output the
specified waveform generated by the waveform
generator. If not using waveform generation, these
terminals enable output compare event output to
use as output compare outputs. When used as a
port, set the corresponding bits in the analog input
enable register (ADER) to “port”.
P36 I/O port
Serial data input pin for UART ch0.
59
58
2D
SIN0
This pin is used continuously when input operation
Port is enabled for UART ch0. In this case, do not use as
inputs a general input pin.
(Hi-Z)
P37 I/O port
60 59 3
D
SOT0
Serial data output pin for UART ch0.
Output operates when UART ch0 output is enabled.
P40 I/O port
61 60 4
D
SCK0
Serial clock I/O pin for UART ch0.
Output operates when UART ch0 clock output is
enabled.
62 to 64,
1 to 3
61 to 64,
1, 2
5 to 10
P41 to
P46
PPG0
to
PPG5
D
I/O ports
Output pins for PPG ch0 to ch5.
The outputs operate when output is enabled for
PPG ch0 to ch5.
4 to 11
3 to 10
P50 to
P57
11 to 18
AN0 to
AN7
F
Analog
inputs
I/O ports
Analog input pins for the A/D converter. Input is
available when the corresponding analog input en-
able register bits are set. (ADER : bit0 to bit7)
Power
12
11
19 AVCC
supply VCC power supply input pin for A/D converter.
input
13
12
20
AVR
G
Refer-
ence volt-
age input
Reference voltage input pin for A/D converter.
Ensure that the voltage does not exceed VCC.
Power
14
13
21
AVSS
supply VSS power supply input pin for A/D converter.
input
* : See “s I/O CIRCUITS” for details of the circuit types.
(Continued)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB90F568.PDF ] | |
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