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T2316160A Schematic ( PDF Datasheet ) - Taiwan Memory Technology

Teilenummer T2316160A
Beschreibung 1024K x 16 DYNAMIC RAM FAST PAGE MODE
Hersteller Taiwan Memory Technology
Logo Taiwan Memory Technology Logo 




Gesamt 13 Seiten
T2316160A Datasheet, Funktion
tm TE
CH
DRAM
T2316160A
1024K x 16 DYNAMIC RAM
FAST PAGE MODE
FEATURES
Industry-standard x 16 pinouts and timing
functions.
Single 5V (±10%) power supply.
www.DataSheet4U.com
All device pins are TTL- compatible.
1K-cycle refresh in 16ms.
Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
BYTE WRITE and BYTE READ access cycles.
OPTION
TIMING
MARKING
45ns -45
60ns -60
PACKAGE
42-pin SOJ
J
44/50-pin TSOPII S
PIN ASSIGNMENT ( Top View )
VDD
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 Vss
41 DQ15
40 DQ14
39 DQ13
38 DQ12
37 Vss
36 DQ11
35 DQ10
34 DQ9
33 DQ8
32 NC
31 CASL
30 CASH
29 OE
28 A9
27 A8
26 A7
25 A6
24 A5
23 A4
22 Vss
GENERAL DESCRIPTION
The T2316160A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316160A has both
BYTE WRITE and WORD WRITE access cycles
via two CAS pins. It offers Fast Page mode with
Extended Data Output.
The T2316160A CAS function and timing are
determined by the first CAS to transition low and
by the last to transition back high. Use only one of
the two CAS and leave the other staying high
during WRITE will result in a BYTE WRITE.
CASL to transition low in a WRITE cycle will
write data into the lower byte (DQ0~DQ7), and
CASH transiting low will write data into the
upper byte (DQ8~DQ15).
VDD
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VDD
15
16
17
18
19
20
21
22
23
24
25
50 Vss
49 DQ15
48 DQ14
47 DQ13
46 DQ12
45 Vss
44 DQ11
43 DQ10
42 DQ9
41 DQ8
40 NC
36 NC
35 CASL
34 CASH
33 OE
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 Vss
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:A






T2316160A Datasheet, Funktion
tm TE
CH
Notes:
1. An initial pause of 200us is required after
power-up followed by eight RAS refresh
cycles ( RAS only or CBR) before proper
device operation is assured. The eight RAS
cycle wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
2. VIH(2.4V) and VIL(0.8V) are reference levels
www.DataSheet4U.cofomr measuring timing of input signals.
Transition times are measured between
VIH(2.4V) and VIL(0.8V).
3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.
4. Assume that tRCD < tRCD(max). If tRCD is
greater than the maximum recommended value
shown in this table, tRAC will increase by the
amount that tRCD exceeds the value shown.
5. Assume that tRCD tRCD(max) .
6. Enables on-chip refresh and address counters.
7. Operation within the tRCD(max) limit ensures
that tRAC(max) can be met. tRCD(max) is
specified as a reference point only; if tRCD is
greater than the specified tRCD(max) limit,
access time is controlled by tCAC.
8. Operation within the tRAD limit ensures that
tRAC(max) can be met. tRAD(max) is
specified as a reference point only; if tRAD is
greater than the specified tRAD(max) limit,
access time is controlled by tAA.
9. Either tRCH or tRRH must be satisfied for a
READ cycle.
10. tOFF1(max) defines the time at which the
output achieves the open circuit condition; it is
not a reference to VOH or VOL.
T2316160A
11. tWCS, tRWD, tAWD and tCWD are
restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
only. If tWCS tWCS(min), the cycle is an
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If tRWD tRWD(min), tAWD
tAWD(min) and tCWD tCWD(min), the
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until CAS and
RAS or OE go back to VIH) is indeterminate.
OE held high and WE taken low after CAS
goes low result in a LATE WRITE ( OE -
controlled) cycle.
12. These parameters are referenced to CAS
leading edge in EARLY WRITE cycles and
WE leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
13. During a READ cycle, if OE is low then
taken HIGH before CAS goes high, I/O goes
open, if OE is tied permanently low, a LATE
WRITE or READ-MODIFY-WRITE
operation is not possible.
14. WRITE command is defined as WE going
low.
15. LATE WRITE and READ-MODIFY-WRITE
cycles must have both tOFF2 and tOEH met
( OE high during WRITE cycle) in order to
ensure that the output buffers will be open
during the WRITE cycles.
16. The I/Os open during READ cycles once
tOFF1 or tOFF2 occur.
Taiwan Memory Technology, Inc. reserves the right P. 6
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:A

6 Page









T2316160A pdf, datenblatt
tm TE
CH
PACKAGE DIMENSIONS
42-LEAD SOJ DRAM (400 mil)
www.DataSheet4U.com
T2316160A
SYMBOL
A
A1
A2
B
b
c
D
E
e
E1
L
y
DIMENSIONS IN INCHES
0.128~0.148
0.025(MIN)
0.105~0.115
0.026~0.032
0.015~0.020
0.007~0.013
1.070~1.080
0.395~0.405
0.050
0.435~0.445
0.082(MIN)
0.004(MAX)
DIMENSIONS IN MM
3.251~3.759
0.635(MIN)
2.657~2.920
0.660~0.813
0.381~0.508
0.178~0.330
27.178~27.432
10.033~10.287
1.270
11.049~11.303
2.083(MIN)
0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 12
to change products or specifications without notice.
Publication Date: APR. 2002
Revision:A

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