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CY14E064L Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer CY14E064L
Beschreibung 64 Kbit (8K x 8) nvSRAM
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 17 Seiten
CY14E064L Datasheet, Funktion
CY14E064L
64 Kbit (8K x 8) nvSRAM
Features
25 ns and 45 ns access times
Hands off automatic STORE on power down with external
68 mF capacitor
STORE to QuantumTrap® non-volatile elements is initiated
by software, hardware or AutoStore on power down
RECALL to SRAM initiated by software or power up
www.DataSheet4UUn.cliommited READ, WRITE and RECALL cycles
10 mA typical ICC at 200 ns cycle time
1,000,000 STORE cycles to QuantumTrap
100 year data retention to QuantumTrap
Single 5V operation +10%
Commercial temperature
SOIC package
RoHS compliance
Functional Description
The Cypress CY14E064L is a fast static RAM with a
non-volatile element in each memory cell. The embedded
non-volatile elements incorporate QuantumTrap technology
producing the world’s most reliable non-volatile memory. The
SRAM provides unlimited read and write cycles, while
independent, non-volatile data resides in the highly reliable
QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control. A hardware STORE is
initiated with the HSB pin.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Quantum Trap
128 X 512
STORE
STATIC RAM
ARRAY
128 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A0 A12
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06543 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 7, 2007
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CY14E064L Datasheet, Funktion
CY14E064L
Preventing STOREs
The STORE function is disabled by holding HSB high with a
driver capable of sourcing 30 mA at a VOH of at least 2.2V,
because it has to overpower the internal pull down device. This
device drives HSB LOW for 20 μs at the onset of a STORE.
Table 1. Hardware Mode Selection
When the CY14E064L is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on VCAP)
and VCC crosses VSWITCH on the way down, the CY14E064L
attempts to pull HSB LOW. If HSB does not actually get below
VIL, the part stops trying to pull HSB LOW and abort the
STORE attempt.
CE
H
L
L
www.DataSheet4U.com X
L
L
WE
HSB
A12–A0
Mode
IO Power
X
H
X
Not Selected
Output High Z
Standby
H
H
X
Read SRAM
Output Data
Active
L
H
X
Write SRAM
Input Data
Active
X
L
X
Non-volatile STORE Output High Z
ICC2
H
H
0000
Read SRAM
Output Data
Active
1555
0AAA
Read SRAM
Read SRAM
Output Data
Output Data
ICC2
1FFF
Read SRAM
Output Data
10F0
Read SRAM
Output Data
0F0F
Non-volatile STORE Output High Z
H
H
0000
Read SRAM
Output Data
Active
1555
Read SRAM
Output Data
0AAA
Read SRAM
Output Data
1FFF
Read SRAM
Output Data
10F0
Read SRAM
Output Data
0F0E
Non-volatile RECALL Output High Z
Document Number: 001-06543 Rev. *D
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CY14E064L pdf, datenblatt
CY14E064L
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle 1: WE Controlled [14,15]
ADDRESS
tWC
CE
www.DataSheet4U.com
WE
tSCE
tHA
tAW
tSA
tPWE
DATA IN
DATA OUT
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
ADDRESS
CE
WE
DATA IN
Figure 8. SRAM Write Cycle 2: CE Controlled
tWC
t t tSA SCE HA
tAW
tPWE
tSD
DATA VALID
tHD
Note
15. CE or WE must be greater than VIH during address transitions.
Document Number: 001-06543 Rev. *D
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