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71P71204S250BQ8 Schematic ( PDF Datasheet ) - IDT

Teilenummer 71P71204S250BQ8
Beschreibung IDT71P71204S250BQ8
Hersteller IDT
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Gesamt 24 Seiten
71P71204S250BQ8 Datasheet, Funktion
Advance
18Mb Pipelined
DDR™II SRAM
Burst of 2
Information
IDT71P71204
IDT71P71104
IDT71P71804
Features
x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
x Common Read and Write Data Port
x Dual Echo Clock Output
x 2-Word Burst on all SRAM accesses
x Multiplexed Address Bus
- One Read or One Write request per clock cycle
www.DataSheet4U.coxm DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
x Depth expansion through Control Logic
x HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
x Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70
ohms
x 1.8V Core Voltage (VDD)
x 165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
x JTAG Interface
IDT71P71604
Description
The IDT DDRIITM Burst of two SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization of the bandwidth on the data bus by pass-
ing two data items per clock cycle. The address bus operates at single
data rate speeds, allowing the user to fan out addresses and ease
system design while maintaining maximum performance on data trans-
fers.
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, indepen-
dent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the DDRII has an output “echo” clock,
CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and BWx or NWx), the
address, and the first word of the data burst during a write operation.
Functional Block Diagram
DATA
REG
(Note2)
SA
SA0
ADD
REG
(Note2)
LD
R/W
BWx
(Note3)
CTRL
LOGIC
(Note 1)
WRITE DRIVER
18M
MEMORY
ARRAY
(Note1)
(Note4)
(Note1) DQ
K CLK
K GEN
C SELECT OUTPUT CONTROL
C
CQ
CQ
Notes
6112 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ DSC-6112/00






71P71204S250BQ8 Datasheet, Funktion
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration 2M x 9
1 2 3 4 5 6 7 8 9 10 11
A CQ VSS/ SA R/W NC K NC LD SA VSS/ CQ
SA (2)
SA (1)
B NC NC NC SA NC K BW SA NC NC DQ3
www.DataSheet4U.com
C NC NC NC VSS SA SA SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD VDDQ VDDQ VREF
ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ1 NC
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L
NC DQ6
NC VDDQ VSS VSS VSS VDDQ NC
NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA C SA SA NC NC DQ8
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
6112 tb l 12a
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
165-ball FBGA Pinout
TOP VIEW
6.642

6 Page









71P71204S250BQ8 pdf, datenblatt
IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
Advance Information
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
P aram eter
S ym bol
Test Conditions
Min Max Unit Note
Inp ut Le ak ag e Curre nt
IIL V DD = M ax VIN = V SS to V DDQ
-10 +10 µA
Outp ut Le akag e Curre nt
IOL Output Dis abled
-10 +10 µA
Op e rating Curre nt
(x36,x18,x9,x8): DDR
www.DataSheet4U.com
Stand b y Curre nt: NOP
Output High Voltage
333M HZ
-
TB D
VDD = Max,
IDD IO UT = 0mA (o utp uts o p e n),
Cyc le Tim e > tKHKH M in
300M HZ
250M HZ
200MHz
-
-
-
TB D
TB D
TB D
167MHz
-
TB D
333M HZ
-
TB D
De vice De se le cte d (in NOP state ), 300M HZ
IS B1
IO UT = 0mA (outputs o pen),
f=M ax,
250M HZ
All Inputs <0.2V or > V DD -0.2V 200M Hz
-
-
-
TB D
TB D
TB D
167MHz
-
TB D
V O H1 RQ = 250Ω, IOH = -15m A
VDDQ/2-0.12 VDDQ /2+0.12
mA
mA
V
1
2
3,7
Output Low Voltag e
V OL1 RQ = 250Ω, IOH = 15mA
VDDQ/2-0.12 VDDQ /2+0.12
V
4,7
Output High Voltage
VO H2 IOH = -0.1m A
VDDQ-0.2
V DD Q
V
5
Output Low Voltag e
VOL2 IOL = 0.1m A
VSS 0.2
V
6
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175< RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175< RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
6112 tb l 10 c
61.422

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