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QG80331M550 Schematic ( PDF Datasheet ) - Intel

Teilenummer QG80331M550
Beschreibung I/O Processor
Hersteller Intel
Logo Intel Logo 




Gesamt 30 Seiten
QG80331M550 Datasheet, Funktion
www.DataSheet4U.com
Intel® 80331 I/O Processor
Specification Update
April 2006
The Intel® 80331 I/O Processor may contain design defects or errors known as errata that may
cause the product to deviate from published specifications. Current characterized errata are doc-
umented in this specification update.
Order Number: 273930-021US






QG80331M550 Datasheet, Funktion
Intel® 80331 I/O Processor
Revision History
Date
January 2005
November 2004
www.DataSheet4U.com
September 2004
August 2004
June 2004
May 2004
April 2004
Version
011
010
009
008
007
006
005
Description
Added:
• Non-Core Errata 57
• Specification Clarification 26
• Documentation Change 13 and 14
Added:
• Non-Core Errata 56
• Specification Clarification 25
Added:
• Specification Clarification 23 and 24.
• Specification Change 18.
• Documentation Change 12.
Updated:
• Specification Change 11 and Specification Clarifications 13 and 22.
Added:
• D-0 stepping information.
• Non-Core Errata 55.
• Specification Clarification 21 and 22.
• Specification Change 17.
Updated:
• Non-Core Errata 51 and 54.
Added:
• Non-Core Errata 52 through 54.
• Specification Clarification 19 and 20.
• Documentation Change 11.
Added:
• Non-Core Errata 49 through 51
• Specification Clarification 17 and 18
• Specification Change 14 through 16
• Documentation Change 10
Updated:
• Spec Change 12; Spec Clarification 13
Added:
• Non-Core Errata 46 through 48.
• Specification Clarification 13 through 16.
• Documentation Change 8 and 9.
• Added C-1 to errata table
Updated:
• Non-Core Errata 45.
• Specification Change 11.
• Specification Clarification 11 and 12.
• Documentation Change 3.
• Status information for Non-Core Errata.
6 Specification Update

6 Page









QG80331M550 pdf, datenblatt
Intel® 80331 I/O Processor
Summary Table of Changes
Non-Core Errata (Sheet 3 of 3)
No.
53
54
55
56
www.DataSheet4U.com
57
58
59
60
61
62
63
Steppings
Page Status
A-1 B-0 C-0 C-1 D-0 D-1
Errata
X
X
X
X
X
X
38
No Fix
PCI-to-PCI read flow-through with destination TRDY# stalls
can cause data corruption
XXXX
38 Fixed S_PCIXCAP PCI mode threshold is too high
X X X X X X 39 No Fix No support for burst I/O and configuration read/writes
X
X
X
X
X
X
39
No Fix
Read flow through hangs due to disconnect without data at
a buffer boundary.
X X X X X X 39 No Fix P_SERR# not asserted for parity error on AD[63:32]
X
X
X
X
X
X
39
No Fix
Bus Interface Unit (BIU) claims DAC addresses in the
range of the Memory Mapped Registers (MMR
X
X
X
X
X
X
40
No Fix
PCIX-to-PCI Memory Read issued as 32-bit, then retried as
64-bit
Tc1(min) of the PCI-X clock observed to be marginally less
X X X X X X 41 No Fix than the requirement specified for the PCI-X (Mode 1,
class1) clock jitter.
X X X X X X 41 No Fix I2C Control Register reset bit does not function
X 41 Fixed Internal Clock Misalignment Can Cause Processor Hang.
X X X X X X 41 No Fix Spurious DMA0 End-Of-Transfer Interrupt
12 Specification Update

12 Page





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