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D70325L-8 Schematic ( PDF Datasheet ) - NEC

Teilenummer D70325L-8
Beschreibung UPD70325L-8
Hersteller NEC
Logo NEC Logo 




Gesamt 30 Seiten
D70325L-8 Datasheet, Funktion
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70325
V25+TM
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA
controller, interrupt controller, etc. are all integrated. The µPD70325 is software compatible with the 16/8-bit single-
chip microcontroller µPD70320 (V25TM). The V25+ greatly improves the DMA responsivity and transfer rate compared
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to the V25.
FEATURES
Software compatible with V25
Software compatible with µPD70108/70116 (in native mode) (some instructions added)
Internal 16-bit architecture and external 8-bit data bus
3-stage pipeline method
Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)
: 200 ns/10 MHz (external 20 MHz)
Memory space 1 Mbyte
On-chip RAM : 256 words × 8 bits
Register bank (memory mapped method) : 8 banks
Input port (port T) with comparator : 8 bits
I/O lines (input port : 4 bits, input/output ports : 20 bits)
Serial interface : 2 channels
• Internal dedicated baud rate generator
• Asynchronous mode and I/O interface mode
Interrupt controller
• Programmable priority (8 levels)
• 3 types of interrupt response method
Vectored interrupt function, register bank switching function, macro service function
DRAM and pseudo SRAM refreshing function
DMA controller : 2 channels
• 4 types of DMA transfer mode
• Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release
mode)
Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release
mode, or burst mode)
• Address pointer (linear) : 20 bits
• Terminal counter : 16 bits
16-bit timer : 2 channels
Time base counter (20 bits) : 1 channel
On-chip clock generator
Programmable wait function
Standby function (STOP, HALT)
The information in this document is subject to change without notice.
Document No. U12850EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
The mark shows major revised points.
© 11999965






D70325L-8 Datasheet, Funktion
P20/DMARQ0
P21/DMAAK0
P22/TC0
P23/DMARQ1
P24/DMAAK1
P25/TC1
TxD0
RxD0
P16/SCK0
CTS0
TxD1
RxD1
CTS1
NMI (P10)
P11/INTP0
P12/INTP1
P13/INTP2/INTAK
P14/INT/POLL
PROGRAMMABLE
DMA
CONTROLLER
SERIAL
INTERFACE
BAUD RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
LC
etc.
PSW
PC
ALU
TA
TB
TC
INTERNAL RAM
256 byte
• GR
• MACRO SERVICE
CHANNEL
INSTRUCTION DECODER
MICRO SEQUENSER
MICRO ROM
PFP INC
Note
INTERNAL ROM
8 Kbyte
(reserved)
QUEUE
(6 byte)
16-BIT TIMER
TIME BASE
COUNTER
PORT
PORT with
COMPARATOR
TOUT/P15
REFRQ CLKOUT/P07
P0 P1 P2
PT0 to 7 VTH
Note The internal ROM of 8 Kbytes is reserved for specific use such as testing and not user-accessible.
CG
A0 to A19
RESET
HLDAK/P26
HLDRQ/P27
READY/P17
MREQ
MSTB
R/W
IOSTB
POLL/INT/P14
EA
D0 to D7
X1
X2
VDD
GND

6 Page









D70325L-8 pdf, datenblatt
µPD70325
2.2 Instruction Set Operation
Identifier
reg, reg’
reg8, reg8’
reg16, reg16’
dmem
mem
mem8
mem16
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sfr
imm
imm3
imm4
imm8
imm16
acc
sreg
src-table
src-block
dst-block
near-proc
far-proc
near-label
short-label
far-label
memptr16
memptr32
regptr16
pop-value
fp-op
R
Table 2-1. Operand Identifier
Description
8-/16-bit general register
8-bit general register
16-bit general register
8-/16-bit memory location
8-/16-bit memory location
8-bit memory location
16-bit memory location
32-bit memory location
8-bit special function register location
Constant within 0 to FFFFH
Constant within 0 to 7
Constant within 0 to FH
Constant within 0 to FFH
Constant within 0 to FFFFH
Register AW or AL
Segment register
256-byte conversion table name
Register IX-addressed block name
Register IY-addressed block name
Procedure in the current program segment
Procedure in another program segment
Label in the current program segment
Label within end of instruction to –128 to +127 bytes
Label in another program segment
Word including location offset in the current program segment to which control is to be passed
Double-word including location offset in another program segment to which control is to be passed
and segment base address
16-bit general register including location offset in another program segment to which control is to be
passed
Number of bytes to be abandoned from stack (0 to 64K, normally even number)
Immediate value to judge instruction code of external floating point operation chip
Register set
12

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