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Número de pieza | CY7C1049BN | |
Descripción | 512K x 8 Static RAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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No Preview Available ! 512 K × 8 Static RAM
Features
■ High speed
❐ tAA = 17 ns
■ Low active power
❐ 1073 mW (max.)
■ Low CMOS standby power
❐ 2.75 mW (max.)
■ 2.0 V data retention (400 W at 2.0 V retention)
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
Logic Block Diagram
CY7C1049BN
512 K × 8 Static RAM
Functional Description
The CY7C1049BN is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A18).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1049BN is available in a standard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
For a complete list of related documentation, click here.
A0
A1
A2
AA34
AA56
AAA978
A10
CE
WE
OE
INPUT BUFFER
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-76449 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 18, 2014
1 page CY7C1049BN
Capacitance
Parameter [2]
Description
CIN
COUT
Input capacitance
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1 481
5V
R1 481
5V
3.0V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
OUTPUT
R2
255
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
GND
3 ns
ALL INPUT PULSES
90%
10%
90%
10%
3 ns
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167
1.73V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
VDR
ICCDR
tCDR[2]
tR[4]
VCC for Data Retention
Data Retention Current
Commercial L
Chip Deselect to Data Retention
Time
Operation Recovery Time
Conditions [3]
VCC = VDR = 3.0 V,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
Min
2.0
–
0
tRC
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
VDR > 2 V
tCDR
CE
3.0 V
tR
Max Unit
–V
200 A
– ns
– ns
Notes
2. Tested initially and after any design or process changes that may affect these parameters.
3. No input may exceed VCC + 0.5 V.
4. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds.
Document Number: 001-76449 Rev. *B
Page 5 of 15
5 Page CY7C1049BN
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products.
Speed
(ns)
Ordering Code
17 CY7C1049BNL-17VC
Package
Diagram
Package Type
51-85090 36-pin (400-Mil) Molded SOJ
Operating
Range
Commercial L
Ordering Code Definitions
CY 7 C 1 04 9 BN L - 17 V C
Temperature Grade:
C = Commercial
Package Type:
V = 36-pin Molded SOJ
Speed Grade: 17 ns
Low Power
Process Technology: BN = 180 nm
Bus width: 9 = × 8
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-76449 Rev. *B
Page 11 of 15
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet CY7C1049BN.PDF ] |
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