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79RC32355 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 79RC32355
Beschreibung IDT Interprise Integrated Communications Processor
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
79RC32355 Datasheet, Funktion
IDTTM InterpriseTM Integrated
Communications Processor
www.DataSheet4U.com
79RC32355
Features List
RC32300 32-bit Microprocessor
– Enhanced MIPS-II ISA
– Enhanced MIPS-IV cache prefetch instruction
– DSP Instructions
– MMU with 16-entry TLB
– 8KB Instruction Cache, 2-way set associative
– 2KB Data Cache, 2-way set associative
– Per line cache locking
– Write-through and write-back cache management
– Debug interface through the EJTAG port
– Big or Little endian support
Interrupt Controller
– Allows status of each interrupt to be read and masked
I2C
– Flexible I2C standard serial interface to connect to a variety of
peripherals
– Standard and fast mode timing support
– Configurable 7 or 10-bit addressable slave
UARTs
– Two 16550 Compatible UARTs
– Baud rate support up to 1.5 Mb/s
Counter/Timers
– Three general purpose 32-bit counter/timers
General Purpose I/O Pins (GPIOP)
– 36 individually programmable pins
– Each pin programmable as input, output, or alternate function
– Input can be an interrupt or NMI source
– Input can also be active high or active low
Block Diagram
SDRAM Controller
– 2 memory banks, non-interleaved, 512 MB total
– 32-bit wide data path
– Supports 4-bit, 8-bit, and 16-bit wide SDRAM chips
– SODIMM support
– Stays on page between transfers
– Automatic refresh generation
Peripheral Device Controller
– 26-bit address bus
– 32-bit data bus with variable width support of 8-,16-, or 32-bits
– 8-bit boot ROM support
– 6 banks available, up to 64MB per bank
– Supports Flash ROM, PROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation, Intel or Motorola style
– Write protect capability
– Direct control of optional external data transceivers
System Integrity
– Programmable system watchdog timer resets system on time-
out
– Programmable bus transaction times memory and peripheral
transactions and generates a warm reset on time-out
DMA
– 16 DMA channels
– Services on-chip and external peripherals
– Supports memory-to-memory, memory-to-I/O, and I/O-to-I/O
transfers
– Supports flexible descriptor based operation and chaining via
linked lists of records (scatter / gather capability)
– Supports unaligned transfers
– Supports burst transfers
RC32300
CPU Core
ICE EJTAG MMU
D. Cache I. Cache
Interrupt
Controller
:
:
3 Counter
Timers
Watchdog
Timer
10/100
Ethernet
Interface
USB
Interface
16 Channel
DMA
Controller
Arbiter
Ext. Bus
Master
SDRAM &
Device
Controller
I2C
Controller
2 UARTS
(16550)
GPIO
Interface
TDM
Interface
ATM
Interface
Memory & I2C Bus
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins TDM Bus
Figure 1 RC32355 Internal Block Diagram
Utopia 1 / 2
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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May 25, 2004
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79RC32355 Datasheet, Funktion
IDT 79RC32355
Name
Type I/O Type
Description
www.DataSheet4U.com
RWN O High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write
transaction. A high level indicates a read from an external device, a low level indicates a write to an external device.
OEN O High Drive Output Enable. This signal is asserted low when data should be driven by an external device during device read transac-
tions on the memory and peripheral bus.
BWEN[3:0]
O High Drive SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables. These signals are used as data input/output masks
during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and
peripheral bus. They are active low.
BWEN[0] corresponds to byte lane MDATA[7:0].
BWEN[1] corresponds to byte lane MDATA[15:8].
BWEN[2] corresponds to byte lane MDATA[23:16].
BWEN[3] corresponds to byte lane MDATA[31:24].
SDCSN[1:0]
O High Drive SDRAM Chip Select. These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is
asserted low during an access to the selected SDRAM.
RASN
O High Drive SDRAM Row Address Strobe. The row address strobe asserted low during memory and peripheral bus SDRAM transac-
tions.
CASN
O High Drive SDRAM Column Address Strobe. The column address strobe asserted low during memory and peripheral bus SDRAM
transactions.
SDWEN
O High Drive SDRAM Write Enable. Asserted low during memory and peripheral bus SDRAM write transactions.
CKENP
O Low Drive SDRAM Clock Enable. Asserted high during active SDRAM clock cycles.
Primary function: General Purpose I/O, GPIOP[21].
SDCLKINP
I STI SDRAM Clock Input. This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32355
on the rising edge of this clock.
ATM Interface
ATMINP[11:0]
I STI ATM PHY Inputs. These pins are the inputs for the ATM interface.
ATMIOP[1:0]
I/O Low Drive ATM PHY Bidirectional Signals. These pins are the bidirectional pins for the ATM interface.
with STI
ATMOUTP[9:0]
O Low Drive ATM PHY Outputs. These pins are the outputs for the ATM interface.
TXADDR[1:0]
O Low Drive ATM Transmit Address [1:0]. 2-bit address bus used for transmission in Utopia-2 mode.
TXADDR[0] Primary function: General purpose I/O, GPIOP[22].
TXADDR[1] Primary function: General purpose I/O, GPIOP[23].
RXADDR[1:0]
O Low Drive ATM Receive Address [1:0]. 2-bit address bus for receiving in Utopia-2 mode.
RXADDR[0] Primary function: General purpose I/O, GPIOP[24].
RXADDR[1] Primary function: General purpose I/O, GPIOP[25].
TDM Bus
TDMDOP
O High Drive TDM Serial Data Output. Serial data is driven by the RC32355 on this signal during an active output time slot. During inac-
tive time slots this signal is tri-stated.
Primary function: General purpose I/O, GPIOP[32].
TDMDIP
I STI TDM Serial Data Input. Serial data is received by the RC32355 on this signal during active input time slots.
Primary function: General purpose I/O, GPIOP[33].
TDMFP
I/O High Drive TDM Frame Signal. A transition on this signal, the active polarity of which is programmable, delineates the start of a new
TDM bus frame. TDMFP is driven if the RC32355 is a master, and is received if it is a slave.
Primary function: General purpose I/O, GPIOP[34].
TDMCLKP
I STI TDM Clock. This input clock controls the rate at which data is sent and received on the TDM bus.
Primary function: General purpose I/O, GPIOP[35].
Table 1 Pin Descriptions (Part 2 of 8)
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79RC32355 pdf, datenblatt
IDT 79RC32355
Name
Type I/O Type
Description
www.DataSheet4U.com
U1CTSN
I STI UART channel 1 clear to send.
Primary function: General Purpose I/O, GPIOP[13]. At reset, this pin defaults to primary function GPIOP[13] if ICE Interface
enable is not selected during reset using the boot configuration.
2nd Alternate function: PC trace clock, EJTAG_DCLK.
1. Schmitt Trigger Input.
2. 2I2C - Bus Specification by Philips Semiconductors.
Table 1 Pin Descriptions (Part 8 of 8)
Boot Configuration Vector
The boot configuration vector is read into the RC32355 during cold reset. The vector defines parameters in the RC32355 that are essential to oper-
ation when cold reset is complete.
The encoding of boot configuration vector is described in Table 2, and the vector input is illustrated in Figure 6.
Signal
MDATA[2:0]
MDATA[3]
MDATA[4]
MDATA[5]
MDATA[7:6]
MDATA[8]
MDATA[9]
MDATA[10]
Name/Description
Clock Multiplier. This field specifies the value by which the system clock (CLKP) is multiplied internally to generate the CPU pipeline clock.
0x0 - multiply by 2
0x1 - multiply by 3
0x2 - multiply by 4
0x3 - reserved
0x4 - reserved
0x5 - reserved
0x6 - reserved
0x7 - reserved
Endian. This bit specifies the endianness of RC32355.
0x0 - little endian
0x1 - big endian
Reserved. Must be set to 0.
Debug Boot Mode. When this bit is set, the RC32355 begins executing from address 0xFF20_0200 rather than 0xBFC0_0000 following a reset.
0x0 - regular mode (processor begins executing at 0xBFC0_0000)
0x1 - debug boot mode (processor begins executing at 0xFF20_0200)
Boot Device Width. This field specifies the width of the boot device.
0x0 - 8-bit boot device width
0x1 - 16-bit boot device width
0x2 - 32-bit boot device width
0x3 - reserved
EJTAG/ICE Interface Enable. When this bit is set, Alternate 2 pin functions EJTAG_PCST[2:0], EJTAG_DCLK, and EJTAG_TRST_N are
selected.
0x0 - GPIOP[31, 13:10] pins behaves as GPIOP
0x1 - GPIOP[31] pin behaves as EJTAG_TRST_N,
GPIOP[12:10] pins behave as EJTAG_PCST[2:0], and
GPIOP[13] pin behaves as EJTAG_DCLK
Fast Reset. When this bit is set, RC32355 drives RSTN for 64 clock cycles, used during test only. Clear this bit for normal operation.
0x0 - Normal reset: RC32355 drives RSTN for minimum of 4096 clock cycles
0x1 - Fast Reset: RC32355 drives RSTN for 64 clock cycles (test only)
DMA Debug Enable. When this bit is set, Alternate 2 pin function, DMAP is selected. DMAP provides the DMA channel number during memory
and peripheral bus DMA transactions.
0x0 - GPIOP[8, 9, 25, 23] pins behave as GPIOP
0x1 - GPIOP[8, 9, 25, 23] pins behave as DMAP[3:0]
Table 2 Boot Configuration Vector Encoding (Part 1 of 2)
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