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Teilenummer | 79RC32334 |
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Beschreibung | IDT Interprise Integrated Communications Processor | |
Hersteller | Integrated Device Technology | |
Logo | ||
Gesamt 30 Seiten IDTTM InterpriseTM Integrated
Communications Processor
79RC32334—Rev. Y
Features
◆ RC32300 32-bit Microprocessor
– Up to 150 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
www.DataSheet4–U.cSomupports big or little endian operation
– MMU with 32 page TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
◆ Local Bus Interface
– Up to 75 MHz operation
– 26-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
◆ Interrupt Controller simplifies exception management
◆ Four general purpose 32-bit timer/counters
Block Diagram
◆ Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
◆ SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 512MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
memories
– Supports 16Mb through 512Mb SDRAM device depths
– Automatic refresh generation
◆ Serial Peripheral Interface (SPI) master mode interface
◆ UART Interface
– Two 16550 compatible UARTs
– Baud rate support up to 1.5 Mb/s
– Modem control signals available on one channel
◆ Memory & Peripheral Controller
– 6 banks, up to 64MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
EJTAG
In-Circuit Emulator Interface
RISCore32300
RC5000
Enhanced MIPS-II ISA Compatible
Integer CPU
CP0
32-page
TLB
2kB
2-set, Lockable
Data Cache
8kB
2-set
Lockable
Instr. Cache
IPBus
Bridge
Interrupt Control
32-bit Timers
DMA Control
Dual UART
IDT
Peripheral
Bus
Programmable I/O
SPI Control
Local
Memory/IO
Control
SDRAM
Control
PCI Bridge
Figure 1 RC32334 Block Diagram
Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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DSC 5701
IDT 79RC32334—Rev. Y
Name
mem_we_n[3:0]
mem_wait_n
mem_245_oe_n
www.DataSheet4U.com
mem_245_dt_r_n
output_clk
PCI Interface
pci_ad[31:0]
pci_cbe_n[3:0]
pci_par
pci_frame_n
pci_trdy_n
pci_irdy_n
pci_stop_n
pci_idsel_n
pci_perr_n
pci_serr_n
pci_clk
Reset
Drive
Type State Strength
Status Capability
Description
Output H
High Memory Write Enable Negated Bus
Signals which bytes are to be written during a memory transaction. Bits act as Byte Enable and
mem_addr[1:0] signals for 8-bit or 16-bit wide addressing.
Input — Memory Wait Negated
Requires external pull-up.
SRAM/IOI/IOM modes: Allows external wait-states to be injected during last cycle before data is sampled.
DPM (dual-port) mode: Allows dual-port busy signal to restart memory transaction.
Alternate function: sdram_wait_n.
Output H
Low Memory FCT245 Output Enable Negated
Controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to
a memory or I/O bank.
Output Z
High Memory FCT245 Direction Xmit/Rcv Negated
Recommend external pull-up.
Alternate function: cpu_dt_r_n. See CPU Core Specific Signals below.
Output cpu_mas
terclk
High Output Clock
Optional clock output.
I/O Z
I/O Z
I/O Z
I/O Z
I/O Z
I/O Z
I/O Z
Input
I/O Z
I/O
Open-
collector
Z
Input
PCI PCI Multiplexed Address/Data Bus
Address driven by Bus Master during initial frame_n assertion, and then the Data is driven by the Bus
Master during writes; or the Data is driven by the Bus Slave during reads.
PCI PCI Multiplexed Command/Byte Enable Bus
Command (not negated) Bus driven by the Bus Master during the initial frame_n assertion. Byte Enable
Negated Bus driven by the Bus Master during the data phase(s).
PCI PCI Parity
Even parity of the pci_ad[31:0] bus. Driven by Bus Master during Address and Write Data phases. Driven
by the Bus Slave during the Read Data phase.
PCI PCI Frame Negated
Driven by the Bus Master. Assertion indicates the beginning of a bus transaction. De-assertion indicates
the last datum.
PCI PCI Target Ready Negated
Driven by the Bus Slave to indicate the current datum can complete.
PCI PCI Initiator Ready Negated
Driven by the Bus Master to indicate that the current datum can complete.
PCI PCI Stop Negated
Driven by the Bus Slave to terminate the current bus transaction.
— PCI Initialization Device Select
Uses pci_req_n[2] pin. See the PCI subsection.
PCI PCI Parity Error Negated
Driven by the receiving Bus Agent 2 clocks after the data is received, if a parity error occurs.
PCI System Error
External pull-up resistor is required.
Driven by any agent to indicate an address parity error, data parity during a Special Cycle command, or
any other system error.
— PCI Clock
Clock for PCI Bus transactions. Uses the rising edge for all timing references.
Table 1 Pin Description (Part 2 of 7)
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6 Page IDT 79RC32334—Rev. Y
Pin Mode Bit
Description
Value Mode Setting
mem_addr[19:18] 9:8 MSB (9)
Boot-Prom Width specifies the memory port
width of the memory space which contains
the boot prom.
00 8 bits
01 16 bits
10 32 bits
11 Reserved
Table 2 Boot-Mode Configuration Settings (Part 2 of 2)
reset_boot_mode Settings
By using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_0000 to base
1900_0000, as required. The RC32334 cold reset-boot mode initialization setting values and mode descriptions are listed below.
Pin Reset Boot Mode
Description
Value Mode Settings
www.DataSheet4U.commem_addr[22:21] 1:0 MSB (1)
Tri-state memory bus and EEPROM bus during cold reset_n
assertion
11 Tri-state_bus_mode
Reserved
10
PCI-boot mode (pci_host_mode must be in satellite mode)
RC32334 will reset either from a cold reset or from a PCI
reset. Boot code is provided via PCI.
01 PCI_boot_mode
Standard-boot mode
00 standard_boot_mode
Boot from the RC32334’s memory controller (typical system).
Table 3 RC32334 reset_boot_mode Initialization Settings
pci_host_mode Settings
During cold reset initialization, the RC32334’s PCI interface can be set to the Satellite or Host mode settings. When set to the Host mode, the CPU
must configure the RC32334’s PCI configuration registers, including the read-only registers. If the RC32334’s PCI is in the PCI-boot mode Satellite
mode, read-only configuration registers are loaded by the serial EEPROM.
Pin Reset Boot Mode
Description
Value Mode Settings
mem_addr[20] PCI host mode
PCI is in satellite mode
1 PCI_satellite
PCI is in host mode (typical system) 0 PCI_host
Table 4 RC32334 pci_host_mode Initialization Settings
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12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ 79RC32334 Schematic.PDF ] |
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