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79RC32K438 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 79RC32K438
Beschreibung IDTTM InterpriseTM Integrated Communications Processor
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 30 Seiten
79RC32K438 Datasheet, Funktion
IDTTM InterpriseTM Integrated
Communications Processor
79RC32438
Features
32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 16KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
www.DataSheet4U.c3o-mentry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– Enhanced JTAG and ICE Interface that is compatible with v2.5
of the EJTAG Specification
DDR Memory Controller
– Supports up to 2GB of DDR SDRAM
– 2 chip selects (each chip select supports 4 internal DDR
banks)
– Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit
devices
– Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
Memory and Peripheral Device Controller
– Provides “glueless” interface to standard SRAM, Flash, ROM,
dual-port memory, and peripheral devices
– Demultiplexed address and data buses: 16-bit data bus, 26-bit
address bus, 6 chip selects, supports alternate bus masters,
control for external data bus buffers
– Supports 8-bit and 16-bit width devices
Automatic byte gathering and scattering
– Flexible protocol configuration parameters: programmable
number of wait states (0 to 63), programmable postread/post-
write delay (0 to 31), supports external wait state generation,
supports Intel and Motorola style peripherals
– Write protect capability per chip select
– Programmable bus transaction timer generates warm reset
when counter expires
– Supports up to 64 MB of memory per chip select
Counter/Timers
– Three general purpose 32-bit counter timers
PCI Interface
– 32-bit PCI revision 2.2 compliant (3.3V only)
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
– I2O “like” PCI Messaging Unit
Block Diagram
MII MII
MIPS-32
CPU Core
Interrupt
Controller
:
:
2 Ethernet
ICE
EJTAG
MMU
D. Cache I. Cache
3 Counter
Timers
10/100
Interfaces
DDR &
DDR
Device
Controllers
IPBusTM
On-Chip
Memory
DMA
Controller
Arbiter
I2C
Controller
2 UARTS
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory & I2C Bus
Peripheral Bus
Ch. 1 Ch. 2
Serial Channels
GPIO Pins SPI Bus
PCI Bus
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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DSC 6148






79RC32K438 Datasheet, Funktion
IDT 79RC32438
Signal
DDRVREF
DDRWEN
PCI Bus
PCIAD[31:0]
www.DataSheet4U.com
PCICBEN[3:0]
PCICLK
PCIDEVSELN
PCIFRAMEN
PCIGNTN[3:0]
PCIIRDYN
PCILOCKN
PCIPAR
PCIPERRN
Type
I
O
Name/Description
DDR Voltage Reference. SSTL_2 DDR voltage reference generated by an
external source.
DDR Write Enable. DDR write enable is asserted during DDR write transac-
tions.
I/O PCI Multiplexed Address/Data Bus. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
I/O PCI Multiplexed Command/Byte Enable Bus. PCI command is driven by the
bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
I PCI Clock. Clock used for all PCI bus transactions.
I/O PCI Device Select. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
I/O PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
I/O PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32438
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32438 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32438 that access to the PCI bus has been granted.
PCIGNTN[1]: this signal takes on the alternate function of PCIEECS and is used
as a PCI Serial EEPROM chip select
PCIGNTN[3:2]: unused and driven high.
Note: When the GPIO register is programmed in the alternate function mode for
bits GPIO [26] and [28], these bits become PCIGNTN [4] and [5] respectively.
I/O PCI Initiator Ready. Driven by the bus master to indicate that the current datum
can complete.
I/O PCI Lock. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
I/O PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
I/O PCI Parity Error. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
Table 1 Pin Description (Part 3 of 9)
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79RC32K438 pdf, datenblatt
IDT 79RC32438
Signal
JTAG_TRST_N
www.DataSheet4U.com
Debug
CPU
INST
Type
I
Name/Description
JTAG Reset. This active low signal asynchronously resets the boundary scan
logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external
pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can access this signal. However, for systems running in func-
tional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
O CPU Transaction. This signal is asserted during all CPU instruction fetches and
data transfers to/from the DDR and devices on the memory and peripheral bus.
The signal is negated during PCI and DMA transactions to/from the DDR and
devices on the memory and peripheral bus.
O Instruction or Data. This signal is driven high during CPU instruction fetches on
the memory and peripheral bus memory or DDR bus.
Table 1 Pin Description (Part 9 of 9)
Pin Characteristics
Note: Some input pads of the RC32438 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32438’s
operation. Also, any input pin left floating can cause a slight increase in power consumption.
Function
Memory and
Peripheral Bus
Pin Name
Type Buffer
I/O Type
Internal
Resistor
BDIRN
BGN
BOEN
BRN
BWEN[1:0]
CSN[5:0]
MADDR[21:0]
MDATA[15:0]
OEN
RWN
WAITACKN
O
LVTTL
High Drive
O
LVTTL
Low Drive
O
LVTTL
High Drive
I LVTTL
STI2
O
LVTTL
High Drive
O
LVTTL
High Drive
O
LVTTL
High Drive
I/O LVTTL High Drive
O
LVTTL
High Drive
O
LVTTL
High Drive
I LVTTL
STI
pull-up
pull-up
Table 2 Pin Characteristics (Part 1 of 4)
Notes1
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