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LM2893M Schematic ( PDF Datasheet ) - National Semiconductor

Teilenummer LM2893M
Beschreibung LM1893/LM2893 Carrier-Current Transceiver
Hersteller National Semiconductor
Logo National Semiconductor Logo 




Gesamt 24 Seiten
LM2893M Datasheet, Funktion
April 1995
LM1893 LM2893 Carrier-Current Transceiver
General Description
Carrier-current systems use the power mains to transfer in-
formation between remote locations This bipolar carrier-
current chip performs as a power line interface for half-du-
plex (bi-directional) communication of serial bit streams of
virtually any coding In transmission a sinusoidal carrier is
FSK modulated and impressed on most any power line via a
rugged on-chip driver In reception a PLL-based demodula-
tor and impulse noise filter combine to give maximum range
A complete system may consist of the LM1893 a COPSTM
controller and discrete components
Features
Y Noise resistant FSK modulation
Y User-selected impulse noise filtering
Y Up to 4 8 kBaud data transmission rate
Y Strings of 0’s or 1’s in data allowed
Y Sinusoidal line drive for low RFI
Y Output power easily boosted 10-fold
Y 50 to 300 kHz carrier frequency choice
Y TTL and MOS compatible digital levels
Y Regulated voltage to power logic
Y Drives all conventional power lines
Applications
Y Energy management systems
Y Home convenience control
Y Inter-office communication
Y Appliance control
Y Fire alarm systems
Y Security systems
Y Telemetry
Y Computer terminal interface
Typical Application
TL H 6750 – 1
FIGURE 1 Block diagram of carrier current chip with a complement of discrete components making a complete
FOe125 kHz fDATAe360 Baud transceiver Use caution with this circuit dangerous line voltage is present
BI-LINETM and COPSTM are trademarks of National Semiconductor Corp
Carrier-Current Transceivers are also called Power Line Carrier (PLC) transceivers
C1995 National Semiconductor Corporation TL H 6750
RRD-B30M115 Printed in U S A






LM2893M Datasheet, Funktion
Application Information
THE DATA PATH
The BI-LINETM chip serves as a power line interface in the
carrier-current transceiver (CCT) system of Figure 3 Figure
4 shows the interface circuit now discussed The controller
may select either the transmit (TX) or receive (RX) mode
Serial data from the controller is used to generate a FSK-
modulated 50 to 300 kHz carrier on the line in the TX mode
In the RX mode line signal passes through the coupling
transformer into the PLL-based receiver The recreated seri-
al bit stream drives the controller
With the IC in the TX mode (pin 5 a logic high) baseband
data to 5 kHz drive the modulator’s Data In pin to generate
a switched 0 978I 1 022I control current to drive the low TC
triangle-wave current-controlled oscillator to g2 2% devia-
tion The tri-wave passes through a differential attenuator
and sine shaper which deliver a current sinusoid through an
automatic level control (ALC) circuit to the gain of 200 cur-
rent output amplifier Drive current from the Carrier I O de-
velops a voltage swing on T1’s (Figure 4 ) resonant tank
proportional to line impedance then passes through the
step-down transformer and coupling capacitor CC onto the
line Progressively smaller line impedances cause reduced
signal swing but never clipping-thus avoiding potential radio
frequency interference When large line impedances threat-
en to allow excessive output swing on pin 10 the ALC
shunts current away from the output amplifier holding the
voltage swing constant and within the amp’s compliance
limit The amplifier is stable with a load of any magnitude or
phase angle
In the RX mode (pin 5 a logic low) the TX sections on the
chip are disabled Carrier signal broad-band noise transient
spikes and power line component impinge of the receiver’s
input highpass filter made up of CC and T1 and the tank
bandpass filter In-band carrier signal band-limited noise
heavily attenuated line frequency component and attenuat-
ed transient energy pass through to produce voltage swing
on the tank swinging about the positive supply to drive the
Carrier I O receiver input The balanced Norton-input limiter
amplifier removes DC offsets attenuates line frequency
performs as a bandpass filter and limits the signal to drive
the PLL phase detector differentially The differential de-
modulated output signal from the phase detector contain-
ing AC and DC data signal noise system DC offsets and a
large twice-the-carrier-frequency component passes
through a 3-stage RC lowpass filter to drive the offset can-
cel circuit differentially The offset cancelling circuit works
by insuring that the (fixed) g50 mV signal delivered to the
data squaring (‘‘slicing’’) comparator is centered around the
0 mV comparator switch point Whenever the comparator
signal plus DC offset and noise moves outside the carefully
matched g50 mV voltage ‘‘window’’ of the offset cancel
circuit it adjusts its DC correction voltage in series with the
differential signal to force the signal back into the window
While the signal is within the g50 mV window the DC offset
is stored on capacitor CM By grace of the highly non-linear
offset hold capacitor charging during offset cancelling the
DC cancellation is done much more quickly than with an AC
coupling capacitor normally used in place of the offset can-
cel circuit Since impulse noise spikes normally ring the sig-
nal symmetrically around 0 V the fully bilateral offset cancel
topology affords excellent noise rejection The switched cur-
rent output of the comparator drives the impulse noise filter
integrator capacitor that rejects all data pulses of less than
the integrator charge time Noise appears as duty-cycle jitter
at the open collector serial data output
Dual-In-Line Package
Top View
Order Number LM1893N
See NS Package Number N18A
TL H 6750 – 2
Small Outline Dual-In-Line Package
Top View
TL H 6750 – 41
Order Number LM2893M or LM2893N
See NS Package Number M20B or N20A
FIGURE 2 Connection Diagrams
TL H 6750 – 3
FIGURE 3 The block diagram of a carrier-current
system using the Bi-Line chip to interface digital
controllers via the power line
Unless otherwise noted all pin references refer to LM1893 but hold true
for equivalent LM2893 pin
6

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LM2893M pdf, datenblatt
Component Selection (Continued)
CF and RF
These phase-locked loop (PLL) loop filter components re-
move some of the noise and most of the 2FO components
present in the demodulated differential output voltage signal
from the phase detector They affect the PLL capture range
loop bandwidth damping and capture time Because the
PLL has an inherent loop pole due to the integrator action of
the ICO (via CO) the loop pole set by CF and the zero set by
RF gives the loop filter a classical 2nd-order response
TL H 6750–18
FIGURE 16 The Norton-input limiter amplifier bandpass
filter line-frequency signal attenuation given CL
TL H 6750–19
FIGURE 17 Find CF given FO Figure 19
gives the maximum data rate
No CF and RF give the most stable PLL with the fastest
response Large CF’s with a too-small RF cause PLL loop
instability leading to poor capture range and poor step re-
sponse or oscillation
Calculation of CF and RF is quite difficult involving not only
the 2nd-order loop step response but also the PLL non-
dominant poles the tuned transformer stepped-frequency
response and the RC lowpass step response (for data rates
approaching 1 kHz) CF and RF values are best found em-
pirically Tolerance is not critical Component values are se-
lected to give the best possible impulse noise rejection
while preserving a g20% capture range and wide stability
margin Figures 17 and 18 give CF and RF values versus FO
where ‘‘fDATA kk MAX DATA RATE’’ means that fDATA
should be less than the maximum data rate in kHz from
Figure 19 divided by 10
Note that CF and RF are a function of data rate only for high
data rates and are not plotted against data rate - as one
might expect The reason for this is important to understand
if the CCT system designer wishes to find CF and RF empiri-
cally Data signal is loosely speaking passed through the
PLL loop and is therefore potentially attenuated if the loop
bandwidth is on the order of the 3rd harmonic of the data
rate or less Overall loop bandwidth is held as low as possi-
ble for maximum noise rejection while passing the data
Loop bandwidth is roughly proportional to the geometric
mean of the unfiltered loop bandwidth and the filter pole set
by CF Therefore CF is related to data rate Unfortunately
the loop capture range falls to critically low values when
large enough values of CF are used to reduce loop band-
width down to the 100’s of Hz range for low data rates The
obvious way out is to then reduce the unfiltered loop band-
width That bandwidth is approximately proportional to the
value of CO For a fixed FO unfiltered loop bandwidth reduc-
tion requires a larger CO and larger control current With this
chip changing the control current is not allowed So one is
forced to choose a CF RF combination with some minimum
capture range say g20% that is within some guardband
from the point of loop instability Happily impulse noise
tends to last only fractions of a millisecond so that the lack
of low bandwidth loop response with low data rates is not a
heavy penalty As long as there is adequate capture range
the impulse noise filter performs admirably Note that reduc-
ing FO will reduce the no-filter loop bandwidth and indeed
the maximum data rate falls below the limit set by the RC
lowpass filter as FO falls below 100 kHz (Figure 19 )
The tuned transformer characteristics will affect the demod-
ulated data waveform more than CF and RF at low data
rates Tank Q and off-tuning will affect overshoot during the
FSK frequency steps This is a property of tuned circuits
The maximum data rate of Figure 19 is measured from the
receiver input to the Data Out and does not include the data
bandwidth reducing effects of TI
CM
Capacitor CM stores a voltage corresponding to a correction
factor required to cancel the phase detector differential out-
put DC offsets The stored voltage is of the DC offset
plus some bias level of about 2 2 V A large CM value in-
creases the time required to bias-up the receive path at the
beginning of transmission A large CM does filter well and
store its bias voltage long Because of the initial random
charge of CM the receiver must be given a data transition to
charge to the proper bias voltage Therefore reducing CM’s
value to one that may be charged in less than 2 bit-times will
not save biasing time and is not recommended
TL H 6750 – 20
FIGURE 18 Find RF given FO with FDATA a parameter
TL H 6750 – 21
FIGURE 19 The maximum data rate versus FO using
loop filter components optimized for max noise
performance while retaining a min g20% capture
range (large signal)
Use Figure 20 to find CM’s value knowing fDATA assuming
the standard 2 bit receive charge time is desired The cap
value and TC are not critical but the capacitor should have
low leakage
12

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