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Teilenummer | H8S2140B |
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Beschreibung | 16-Bit Single-Chip Microcomputer | |
Hersteller | Renesas Technology | |
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Gesamt 70 Seiten To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
www.DataSheet4U.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
www.DataSheet4U.com
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 2.0, 08/02, page iv of xxxviii
6 Page 6.7 Idle Cycle ..........................................................................................................................133
6.8 Bus Arbitration..................................................................................................................134
6.8.1 Priority of Bus Masters ........................................................................................134
6.8.2 Bus Transfer Timing ............................................................................................134
Section 7 Data Transfer Controller (DTC)........................................................ 135
7.1 Features .............................................................................................................................135
7.2 Register Descriptions ........................................................................................................136
7.2.1 DTC Mode Register A (MRA).............................................................................137
7.2.2 DTC Mode Register B (MRB) .............................................................................138
7.2.3 DTC Source Address Register (SAR) ..................................................................138
7.2.4 DTC Destination Address Register (DAR) ..........................................................138
7.2.5 DTC Transfer Count Register A (CRA)...............................................................138
7.2.6 DTC Transfer Count Register B (CRB) ...............................................................139
7.2.7 DTC Enable Registers (DTCER) .........................................................................139
7.2.8 DTC Vector Register (DTVECR) ........................................................................140
7.3 Activation Sources ............................................................................................................140
7.4 Location of Register Information and DTC Vector Table.................................................141
7.5 Operation...........................................................................................................................144
7.5.1 Normal Mode .......................................................................................................145
7.5.2 Repeat Mode ........................................................................................................145
www.DataSh7e.5e.t34U.Bcloomck Transfer Mode ...........................................................................................146
7.5.4 Chain Transfer......................................................................................................147
7.5.5 Interrupts ..............................................................................................................148
7.5.6 Operation Timing .................................................................................................149
7.5.7 Number of DTC Execution States........................................................................150
7.6 Procedures for Using DTC ................................................................................................151
7.6.1 Activation by Interrupt .........................................................................................151
7.6.2 Activation by Software ........................................................................................151
7.7 Examples of Use of DTC ..................................................................................................152
7.7.1 Normal Mode .......................................................................................................152
7.7.2 Software Activation .............................................................................................153
7.8 Usage Notes.......................................................................................................................154
7.8.1 Module Stop Mode Setting ..................................................................................154
7.8.2 On-Chip RAM......................................................................................................154
7.8.3 DTCE Bit Setting .................................................................................................154
7.8.4 Setting Required on Entering Subactive Mode or Watch Mode ..........................154
7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter ........154
Section 8 I/O Ports ............................................................................................ 155
8.1 Overview ...........................................................................................................................155
8.2 Port 1 .................................................................................................................................160
8.2.1 Port 1 Data Direction Register (P1DDR) .............................................................160
Rev. 2.0, 08/02, page x of xxxviii
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