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N80C42 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer N80C42
Beschreibung UNIVERSAL PERIPHERAL INTERFACE CHMOS 8-BIT SLAVE MICROCONTROLLER
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 25 Seiten
N80C42 Datasheet, Funktion
UPI-C42 UPI-L42
UNIVERSAL PERIPHERAL INTERFACE
CHMOS 8-BIT SLAVE MICROCONTROLLER
Y Pin Software and Architecturally
Compatible with all UPI-41 and UPI-42
Products
Y Low Voltage Operation with the UPI-
L42
Full 3 3V Support
Y Hardware A20 Gate Support
Y Suspend Power Down Mode
Y
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Security Bit Code Protection Support
Y 8-Bit CPU plus ROM OTP EPROM RAM
I O Timer Counter and Clock in a
Single Package
Y 4096 x 8 ROM OTP 256 x 8 RAM 8-Bit
Timer Counter 18 Programmable I O
Pins
Y DMA Interrupt or Polled Operation
Supported
Y One 8-Bit Status and Two Data
Registers for Asynchronous Slave-to-
Master Interface
Y Fully Compatible with all Intel and Most
Other Microprocessor Families
Y Interchangeable ROM and OTP EPROM
Versions
Y Expandable I O
Y Sync Mode Available
Y Over 90 Instructions 70% Single Byte
Y Quick Pulse Programming Algorithm
Fast OTP Programming
Y Available in 40-Lead Plastic 44-Lead
Plastic Leaded Chip Carrier and
44-Lead Quad Flat Pack Packages
(See Packaging Spec Order 240800 Package Type P N
and S)
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family It is fabricated on
Intel’s CHMOS III-E process The UPI-C42 is pin software and architecturally compatible with the NMOS UPI
family The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory
array (4K) hardware A20 gate support and lower power consumption inherent to a CHMOS product
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low
voltage 3 3V operation
The UPI-C42 is essentially a ‘‘slave’’ microcontroller or a microcontroller with a slave interface included on the
chip Interface registers are included to enable the UPI device to function as a slave peripheral controller in the
MCS Modules and iAPX family as well as other 8- 16- and 32-bit systems
To allow full user flexibility the program memory is available in ROM and One-Time Programmable EPROM
(OTP)
290414 – 1
Figure 1 DIP Pin
Configuration
290414 – 2
Figure 2 PLCC Pin Configuration
290414 – 3
Figure 3 QFP Pin Configuration
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
December 1995
Order Number 290414-003






N80C42 Datasheet, Funktion
UPI-C42 UPI-L42
If ‘‘EN DMA’’ has been executed P27 becomes
the DACK (DMA ACKnowledge) pin This pin acts
as a chip select input for the Data Bus Buffer
registers during DMA transfers
EN DMA Op Code 0E5H
1 110010 1
6
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7
D7 D0
When EA is enabled on the UPI the program
counter is placed on Port 1 and the lower four
bits of Port 2 (MSB e P23 LSB e P10) On the
UPI this information is multiplexed with PORT
DATA (see port timing diagrams at end of this
data sheet)
The UPI-C42 supports the Quick Pulse Program-
ming Algorithm but can also be programmed
with the Intelligent Programming Algorithm (See
the Programming Section )
PROGRAM MEMORY BANK SWITCH
The switching of 2K program memory banks is ac-
complished by directly setting or resetting the most
significant bit of the program counter (bit 11) see
Figure 5 Bit 11 is not altered by normal increment-
ing of the program counter but is loaded with the
contents of a special flip-flop each time a JMP or
CALL instruction is executed This special flip-flop is
set by executing an SEL PMB1 instruction and reset
by SEL PMB0 Therefore the SEL PMB instruction
may be executed at any time prior to the actual bank
switch which occurs during the next branch instruc-
tion encountered Since all twelve bits of the pro-
gram counter including bit 11 are stored in the
stack when a Call is executed the user may jump to
subroutines across the 2K boundary and the proper
PC will be restored upon return However the bank
switch flip-flop will not be altered on return
UPI-C42 FEATURES
Programmable Memory Size Increase
The user programmable memory on the UPI-C42 will
be increased from the 2K available in the NMOS
product by 2X to 4K The larger user programmable
memory array will allow the user to develop more
complex peripheral control micro-code P2 3 (port 2
bit 3) has been designated as the extra address pin
required to support the programming of the extra 2K
of user programmable memory
The new instruction SEL PMB1 (73h) allows for ac-
cess to the upper 2K bank (locations 2048–4095)
The additional memory is completely transparent to
users not wishing to take advantage of the extra
memory space No new commands are required to
access the lower 2K bytes The SEL PMB0 (63h)
has also been added to the UPI-C42 instruction set
to allow for switching between memory banks
Extended Memory Program
Addressing (Beyond 2K)
For programs of 2K words or less the UPI-C42 ad-
dresses program memory in the conventional man-
ner Addresses beyond 2047 can be reached by ex-
ecuting a program memory bank switch instruction
(SEL PMB0 SEL PMB1) followed by a branch in-
struction (JMP or CALL) The bank switch feature
extends the range of branch instructions beyond
their normal 2K range and at the same time prevents
the user from inadvertently crossing the 2K boundary
6
290414 – 30
Figure 5 Program Counter
INTERRUPT ROUTINES
Interrupts always vector the program counter to lo-
cation 3 or 7 in the first 2K bank and bit 11 of the
program counter is held at ‘‘0’’ during the interrupt
service routine The end of the service routine is sig-
naled by the execution of an RETR instruction Inter-
rupt service routines should therefore be contained
entirely in the lower 2K words of program memory
The execution of a SEL PMB0 or SEL PMB1 instruc-
tion within an interrupt routine is not recommended
since it will not alter PC11 while in the routine but
will change the internal flip-flop
Hardware A20 Gate Support
This feature has been provided to enhance the per-
formance of the UPI-C42 when being used in a key-
board controller application The UPI-C42 design
has included on chip logic to support a hardware
GATEA20 feature which eliminates the need to pro-
vide firmware to process A20 command sequences

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N80C42 pdf, datenblatt
UPI-C42 UPI-L42
www.DataSheet4U.com
Table 3 Signature Mode Table
Address
Test Code Checksum
Intel Signature
User Signature
Test Signature
Security Byte
UPI-C42 Intel Signature
User Defined UPI-C42 OTP EPROM Space
0 0FH
16H 1EH
10H 11H
12H 13H
14H 15H
1FH or 3FH
20H 21H
22H 3EH
Device
Type
ROM OTP
ROM OTP
OTP
ROM OTP
ROM OTP
ROM OTP
ROM OTP
No of
Bytes
25
2
2
2
2
2
30
ACCESS CODE
The following table summarizes the access codes required to invoke the Sync Mode Signature Mode
and the Security Bit respectively Also the programming and verification modes are included for
comparison
Modes
Control Signals
Data Bus
Port 2
Access Code
Port 1
Programming
Mode
Verification
Mode
Sync Mode
T0 RST SS EA PROG VDD VCC 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7
0 0 1 HV 1 VDDH VCC
Address
Addr a0 a1 X X X X X X
0 1 1 HV STB VDDH VCC
Data In
Addr
0 0 1 HV 1 VCC VCC
Address
Addr a0 a1 X X X X X X
1 1 1 HV 1 VCC VCC
Data Out
Addr
STB 0 HV 0 X VCC VCC X X X X X X X X X X X X X X X X X X X
High
Signature Prog 0
Mode
0
Verify 0
1
Security Prog 0
Bit Byte
0
Verify 0
1
0 1 HV 1 VDDH VCC
1 1 HV STB VDDH VCC
0 1 HV 1 VCC VCC
1 1 HV 1 VCC VCC
0 1 HV 1 VDDH VCC
1 1 HV STB VDDH VCC
0 1 HV 1 VCC VCC
1 1 HV 1 VCC VCC
Addr (see Sig Mode Table)
Data In
Addr (see Sig Mode Table)
Data Out
Address
Data In
Address
Data Out
000
000
000
000
000
000
000
000
0 1 1 1 1 XX1
NOTE
1 a0 e 0 or 1 a1 e 0 or 1 a0 must e a1
12

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