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PDF MCP23017 Data sheet ( Hoja de datos )
| Número de pieza | MCP23017 | |
| Descripción | (MCP23017 / MCP23S17) 16-Bit I/O Expander | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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MCP23017/MCP23S17
16-Bit I/O Expander with Serial Interface
Features
• 16-Bit Remote Bidirectional I/O Port:
- I/O pins default to input
• High-Speed I2C Interface (MCP23017):
- 100 kHz
- 400 kHz
- 1.7 MHz
• High-Speed SPI Interface (MCP23S17):
- 10 MHz (maximum)
• Three Hardware Address Pins to Allow Up to
Eight Devices On the Bus
• Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or
open-drain
• INTA and INTB Can Be Configured to Operate
Independently or Together
Package Types
MCP23017
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
VDD
VSS
NC
SCK
SDA
NC
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
A1
A0
SOIC
SPDIP
SSOP
• Configurable Interrupt Source:
- Interrupt-on-change from configured register
defaults or pin changes
• Polarity Inversion Register to Configure the
Polarity of the Input Port Data
• External Reset Input
• Low Standby Current: 1 µA (max.)
• Operating Voltage:
- 1.8V to 5.5V @ -40°C to +85°C
- 2.7V to 5.5V @ -40°C to +85°C
- 4.5V to 5.5V @ -40°C to +125°C
Packages
• 28-pin QFN, 6 x 6 mm Body
• 28-pin SOIC, Wide, 7.50 mm Body
• 28-pin SPDIP, 300 mil Body
• 28-pin SSOP, 5.30 mm Body
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
VDD
VSS
CS
SCK
SI
SO
MCP23S17
• 1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
GPA7
GPA6
GPA5
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
RESET
A2
A1
A0
GPB4
GPB5
GPB6
GPB7
VDD
VSS
NC
28 2726 2524 2322
1 21
2 20
3 19
4
5
EP
29 *
18
17
6 16
7 15
8 9 1011121314
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
QFN
GPB4
GPB5
GPB6
GPB7
VDD
VSS
CS
28 272625242322
1 21
2 20
3 19
4
5
EP
29 *
18
17
6 16
7 15
8 9 10 11121314
GPA4
GPA3
GPA2
GPA1
GPA0
INTA
INTB
* Includes Exposed Thermal Pad; see Table 2-1.
2005-2016 Microchip Technology Inc.
DS20001952C-page 1
1 page  
MCP23017/MCP23S17
1.2 AC Characteristics
FIGURE 1-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
SCL and
SDA pin
MCP23017
VDD
1 k
135 pF
Pin
50 pF
FIGURE 1-2:
VDD
RESET
Internal
RESET
RESET AND DEVICE RESET TIMER TIMING
30 32
Output pin
34
TABLE 1-2: DEVICE RESET SPECIFICATIONS
AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C
Param.
No.
Characteristic
Sym. Min. Typ. (1) Max. Units
Conditions
30 RESET Pulse Width
(Low)
TRSTL
1
— — µs
32 Device Active After Reset THLD
—
0
— ns VDD = 5.0V
high
34 Output High-Impedance TIOZ
—
—
1
µs
From RESET Low
Note 1: This parameter is characterized, not 100% tested.
2005-2016 Microchip Technology Inc.
DS20001952C-page 5
5 Page 
MCP23017/MCP23S17
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PINOUT DESCRIPTION
Pin
Name
QFN
SOIC
SPDIP
SSOP
Pin
Type
Function
GPB0 25 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB1 26 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB2 27 3 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB3 28 4 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB4 1
5 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB5 2
6 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB6 3
7 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB7 4
8 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
VDD 5 9 P Power
VSS 6 10 P Ground
NC/CS 7
11
I NC (MCP23017)/Chip Select (MCP23S17)
SCK
8 12
I Serial clock input
SDA/SI 9
13 I/O Serial data I/O (MCP23017)/Serial data input (MCP23S17)
NC/SO 10 14
O NC (MCP23017)/Serial data out (MCP23S17)
A0
11 15
I Hardware address pin. Must be externally biased.
A1
12 16
I Hardware address pin. Must be externally biased.
A2
13 17
I Hardware address pin. Must be externally biased.
RESET 14 18
I Hardware reset. Must be externally biased.
INTB
15 19
O Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
INTA
16 20
O Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
GPA0 17 21 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA1 18 22 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA2 19 23 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA3 20 24 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA4 21 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA5 22 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA6 23 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA7 24 28 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
EP 29 — — Exposed Thermal Pad. Either connect to VSS, or leave unconnected.
2005-2016 Microchip Technology Inc.
DS20001952C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP23017.PDF ] | |
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