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PDF MT8986 Data sheet ( Hoja de datos )
| Número de pieza | MT8986 | |
| Descripción | Multiple Rate Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
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CMOS ST-BUSTM Family
MT8986
Multiple Rate Digital Switch
Data Sheet
Features
• 256 x 256 or 512 x 256 switching configurations
• 8-bit or 4-bit channel switching capability
• Guarantees frame integrity for wideband
channels
• Automatic identification of ST-BUS/GCI interfaces
• Accepts serial streams with data rates up to
8.192 Mb/s
• Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
• Programmable frame offset on inputs
• Per-channel three-state control
• Per-channel message mode
• Control interface compatible to Intel/Motorola
CPUs
• Low power consumption
Applications
• Medium size digital switch matrices
• Hyperchannel switching (e.g., ISDN H0)
• MVIP™ interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Voice/Data multiplexer
• 32 kbit/s channel switching
September 2011
Ordering Information
MT8986AP1
MT8986APR1
MT8986AL1
MT8986AE1
44 Pin PLCC*
44 Pin PLCC*
44 Pin MQFP*
40 Pin PDIP*
Tubes
Tape & Reel
Trays
Tubes
*Pb Free Matte Tin
-40C to +85C
Description
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of Zarlink's MT8980D Digital Switch
(DX). It is pin compatible with the MT8980D and
retains all of its functionality. This device is designed to
provide simultaneous connections (non-blocking) for
up to 256 64 kb/s channels or blocking connections for
up to 512 64 kb/s channels. The serial inputs and
outputs connected to MT8986 may have 32 to 128
64 kb/s channels per frame with data rates ranging
from 2048 up to 8192 kb/s. The MT8986 provides per-
channel selection between variable and constant
throughput delays allowing voice and grouped data
channels to be switched without corrupting the data
sequence integrity.
In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The MT8986
is ideal for medium size mixed voice and data
switching/processing applications.
VDD VSS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
* STi10
* STi11
* STi12
* STi13
* STi14
* STi15
Serial
to
Parallel
Converter
Timing
Unit
Multiple Buffer Data
Memory
Internal Registers
Microprocessor
Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *
* 44 Pin only
CLK FR AS/ IM DS CS R/W A0/ DTA AD7/
ALE * RD
WR A7
AD0
CSTo
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2011, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
MT8986
Data Sheet
Pin Description (continued)
Pin #
40 44 44
DIP PLCC QFP
Name
Description
40 1 39 CSTo Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256
bits per frame. The level of each bit is determined by the CSTo bit in the Connect
Memory high locations.
- 6 44 AS/ALE Address Strobe or Latch Enable (Input). This input is only used if multiplexed
bus is selected via the IM input pin (44 pin only).
The falling edge of this signal is used to sample the address into the address
latch circuit. In case of non-multiplexed bus, this input is not required and should
be left open.
- 18 12
IM CPU Interface Mode (Input). If HIGH, this input configures MT8986 in
multiplexed microprocessor bus mode. If this input pin is not connected or
grounded, the MT8986 assumes non-multiplexed CPU interface.
- 28 22 STi15/ ST-BUS Input 15 / ST-BUS Output 9 (Input/three-state output). This pin is only
STo9 used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabled in the SCB bits (IMS register), this pin is an input
receiving serial ST-BUS stream 15 at a data rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration
section), this pin is the ST-BUS stream 9 output.
When non-multiplexed bus structure is used, this pin should be left open.
- 40 34 STi14/ ST-BUS Input 14 / ST-BUS Output 8 (Input/three-state output). This pin is only
STo8 used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabled in the SCB bits (IMS register), this pin is an input that
receives serial ST-BUS stream 14 at a data rate of 2.048 Mbit/s.
If Stream Pair Selection capability is enabled (see switching configuration
section), this pin is the ST-BUS stream 8 output.
When non-multiplexed bus structure is used, this pin should be left open.
Device Overview
With the integration of voice, video and data services in the same network, there has been an increasing demand
for systems which ensure that data at N x 64 kbit/s rates maintain sequence integrity while being transported
through time-slot interchange circuits. This requirement demands time-slot interchange devices which perform
switching with constant throughput delay for wideband data applications while guaranteeing minimum delay for
voice channels.
The MT8986 device meets the above requirement and allows existing systems based on the MT8980D to be easily
upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch 32, 64
or N x 64 kbit/s data. The MT8986 can provide frame integrity for data applications and minimum throughput
switching delay for voice applications on a per channel basis.
The serial streams of the MT8986 device can operate at 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125 s
wide frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit
allows the user to interconnect various backplane speeds like 2.048 or 4.096 or 8.192 Mb/s while maintaining the
control of throughput delay function on a per-channel basis.
By using Zarlink Message mode capability, the microprocessor can access input and output time-slots on a per
channel basis to control external circuits or other ST-BUS devices. The MT8986 automatically identifies the polarity
5
Zarlink Semiconductor Inc.
5 Page 
MT8986
Data Sheet
Different I/O Data Rates
Except for 2 Mb/s to 4 Mb/s and 2 Mb/s to 8 Mb/s rate conversion operations, the throughput delay in the MT8986
may vary according to the output stream used for switching.
Table 3b explains the worst case conditions for the throughput delay when different I/O data rate switching
configurations are used.
I/O Data Rate
Configuration
0, 1
Output Stream Used
2, 3 4, 5
6, 7
2 Mb/s to 4 Mb/s dmin=5x 4Mb/s t.s.
dmax=1 fr.+(4x 4Mb/s t.s.)
2 Mb/s to 8 Mb/s dmin=9x 8Mb/s t.s.
dmax=1 fr.+(8x 8Mb/s t.s.)
4 Mb/s to 2 Mb/s dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
8 Mb/s to 2 Mb/s
dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s
t.s.)
dmin=(2x 2Mb/s t.s.)+
(3x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(3x 8Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
(2x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(2x 8Mb/s t.s.)
dmin=(2x 2Mb/s t.s.)+
(1x 8Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s
t.s.)+(1x 8Mb/s t.s.)
Table 3b - Min/Max Throughput Delay Values for Different I/O Rate Applications
Notes: dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.
t.s. = time-slot
fr. = 125 s frame
2 Mb/s t.s. = 3.9 s
4 Mb/s t.s. = 1.95 s
8 Mb/s t.s. = 0.975 s
Constant Throughput Delay mode (V/C bit = 1)
In this mode frame sequence integrity is maintained in both Identical and Different I/O Data Rate operations by
making use of a multiple Data-Memory buffer technique. The input channels written in any of the buffers during
frame N will be read out during frame N+2. In applications at 2.048 Mb/s for instance, the minimum throughput
delay achievable in constant delay mode will be 32 time-slots; for example, when input time-slot 32 (channel 31) is
switched to output time-slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a
frame (channel 0) is switched to the last time-slot in the frame (channel 31), resulting in 94 time-slots of delay.
To summarize, any input time-slot from input frame N will always be switched to the destination time-slot on output
frame N+2. Table 4 describes the MT8986 constant throughput delay values for different data rates.
Data Rate
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Throughput Delay (d)
d=[32 + (32 - IN) + (OUT - 1)]; (expressed in # time-slots)
2.048 Mb/s time-slot: 3.9s
IN: input time-slot (from 1 to 32)
OUT: output time-slot (from 1 to 32)
d=[64 + (64 - IN) + (OUT - 1)]; (expressed in # time-slots)
4.096 Mb/s time-slot: 1.95 s
IN: input time-slot (from 1 to 64)
OUT: output time-slot (from 1 to 64)
d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots)
8.192 Mb/s time-slot: 0.975 s
IN: input time-slot (from 1 to 128)
OUT: output time-slot (from 1 to 128)
Table 4 - Constant Throughput Delay values
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT8986.PDF ] | |
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